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    DETECTION OF CODEWORDS
    21.
    发明申请
    DETECTION OF CODEWORDS 审中-公开

    公开(公告)号：US20200350931A1

    公开(公告)日：2020-11-05

    申请号：US16716735

    申请日：2019-12-17

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel

    IPC: H03M13/39 ,  H03M13/25 ,  H03M13/00

    Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

    MEMORY HAVING DIFFERENT RELIABILITIES
    24.
    发明申请
    MEMORY HAVING DIFFERENT RELIABILITIES 审中-公开

    公开(公告)号：US20200089418A1

    公开(公告)日：2020-03-19

    申请号：US16690384

    申请日：2019-11-21

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Albrecht Mayer

    IPC: G06F3/06 ,  G11C11/56 ,  G06F11/10 ,  G06F11/07

    Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

    Memory device and method for correcting a stored bit sequence
    26.
    发明授权
    Memory device and method for correcting a stored bit sequence 有权

    公开(公告)号：US10109372B2

    公开(公告)日：2018-10-23

    申请号：US15235741

    申请日：2016-08-12

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

    IPC: G11C29/00 ,  G11C29/52 ,  G11C29/42 ,  G11C11/16 ,  G11C29/04

    Abstract: A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (x1/T) assigned to the first memory cells. The frequency (x1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.

    MEMORY DEVICE AND METHOD FOR CORRECTING A STORED BIT SEQUENCE
    28.
    发明申请
    MEMORY DEVICE AND METHOD FOR CORRECTING A STORED BIT SEQUENCE 审中-公开
    存储器件和校正存储器位序列的方法

    公开(公告)号：US20170046223A1

    公开(公告)日：2017-02-16

    申请号：US15235741

    申请日：2016-08-12

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    CPC classification number: G11C29/52 ,  G11C11/1677 ,  G11C29/42 ,  G11C2029/0409

    Abstract: A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (×1/T) assigned to the first memory cells. The frequency (×1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.

    Abstract translation: 存储器装置包括具有与第一存储器单元不同的第一存储单元和第二存储单元的存储器。 在第一存储器单元中存储第一位序列，并且在第二存储器单元中存储第二位序列。 存储装置包括存储器控制器，其被配置为以分配给第一存储器单元的频率（×1 / T）来检查第一位序列。 分配给第一存储器单元的频率（×1 / T）取决于第一存储器单元的可靠性信息项。 在存在错误状态的情况下，存储器控制器被配置以校正第一位序列的错误位并且将至少校正的位回写到存储器中。 基于第二存储器单元的可靠性信息项，比第一比特序列更频繁地检查第二比特序列。

    Word line address scan
    29.
    发明授权
    Word line address scan 有权
    字线地址扫描

    公开(公告)号：US09343179B2

    公开(公告)日：2016-05-17

    申请号：US14132053

    申请日：2013-12-18

    Applicant: Infineon Technologies AG

    Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

    IPC: G11C29/00 ,  G11C29/02 ,  G06F11/10

    CPC classification number: G11C29/024 ,  G06F11/1076

    Abstract: A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.

    Abstract translation: 公开了一种执行三次扫描以测试地址解码器和字线驱动电路的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。

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