公开(公告)号：US08889543B2

公开(公告)日：2014-11-18

申请号：US13795807

申请日：2013-03-12

申请人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

发明人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

摘要： A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

摘要翻译： 制造半导体器件的方法包括在衬底上形成开关器件。 在具有开关装置的基板中形成下部结构。 下导电层形成在下结构上。 牺牲掩模图案形成在下导电层上。 通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。 在具有较低导电图案的基板上形成层间绝缘层。 通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。 通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。 在开口中形成与下导电图案自对准的上导电图案。

公开(公告)号：US06806135B2

公开(公告)日：2004-10-19

申请号：US10327902

申请日：2002-12-26

申请人： Hyun-Seok Lim ,  In-Sun Park ,  Sang-Bum Kang ,  Jong-sik Chun ,  Seong-Geon Park ,  In-Su Ha

发明人： Hyun-Seok Lim ,  In-Sun Park ,  Sang-Bum Kang ,  Jong-sik Chun ,  Seong-Geon Park ,  In-Su Ha

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/32051 ,  H01L27/10852 ,  H01L28/60

摘要： The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.

摘要翻译： 本发明公开了一种制造具有上电容电极和节点电阻器的半导体器件的方法，包括以第一沉积速率在晶片的边缘部分上沉积薄膜，并以第二沉积速率沉积在晶片的中心部分上 晶圆以形成上电容电极和节点电阻，从而提高上电容器电极的台阶覆盖，同时改善节点电阻器的电阻分布。

公开(公告)号：US08547747B2

公开(公告)日：2013-10-01

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C16/04

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅极电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120120728A1

公开(公告)日：2012-05-17

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US20090008623A1

公开(公告)日：2009-01-08

申请号：US12216004

申请日：2008-06-27

申请人： Hyun-Seok Lim ,  In-Sun Park ,  Gyu-Hwan Oh ,  Do-Hyung Kim ,  Shin-Jae Kang

发明人： Hyun-Seok Lim ,  In-Sun Park ,  Gyu-Hwan Oh ,  Do-Hyung Kim ,  Shin-Jae Kang

IPC分类号： H01L47/00 ,  H01L21/311

CPC分类号： H01L21/28518 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas.

摘要翻译： 提供使用电阻材料制造非易失性存储器件和非易失性存储器件的方法。 根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底上形成至少一个半导体图案，在至少一个半导体图案上形成金属层，形成混合相金属硅化物层，其中至少 两相共存，通过在基板上进行至少一次热处理，使得至少一个半导体图案可与金属层反应，并使基板暴露于蚀刻气体。

公开(公告)号：US20080230373A1

公开(公告)日：2008-09-25

申请号：US12051043

申请日：2008-03-19

申请人： Do-Hyung Kim ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Gyu-Hwan Oh

发明人： Do-Hyung Kim ,  Shin-Jae Kang ,  In-Sun Park ,  Hyun-Seok Lim ,  Gyu-Hwan Oh

IPC分类号： C23C14/34

CPC分类号： C23C14/3414 ,  C23C14/0623 ,  G11B7/2433 ,  G11B7/252 ,  G11B2007/24312 ,  G11B2007/24314 ,  G11B2007/24316 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.

摘要翻译： 本发明提供了形成相变材料层的方法，包括在碲被挥发并且锑不挥发的温度下提供包括锗（Ge），锑（Sb）和碲（Te）的基板和硫族化物靶，以及 进行溅射工艺以在衬底上形成包括硫族化物材料的相变材料层。 还提供了制造使用其的相变存储器件的方法。

公开(公告)号：US20060113615A1

公开(公告)日：2006-06-01

申请号：US11284653

申请日：2005-11-22

申请人： Eung-Joon Lee ,  Hyun-Young Kim ,  In-Sun Park ,  Hyun-Deok Lee

发明人： Eung-Joon Lee ,  Hyun-Young Kim ,  In-Sun Park ,  Hyun-Deok Lee

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/3003 ,  H01L21/28518 ,  H01L21/28556 ,  H01L29/665 ,  H01L29/78

摘要： A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.

公开(公告)号：US07005373B2

公开(公告)日：2006-02-28

申请号：US10790921

申请日：2004-03-02

申请人： Eung-Joon Lee ,  In-Sun Park ,  Kwan-Jong Roh

发明人： Eung-Joon Lee ,  In-Sun Park ,  Kwan-Jong Roh

IPC分类号： H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

摘要翻译： 在衬底的第一和第二区域上分别形成包括第一栅极和第一间隔物的第一栅极结构，以及包括第二栅电极和第二间隔物的第二栅极结构。 将第一和第二间隔物移除到不同的深度，使得第一和第二栅极的侧部具有不同的暴露厚度。 在包括第一和第二栅极结构的第一和第二区域上形成金属硅化物层。 形成在第二栅电极上的金属硅化物层具有大于形成在第一栅电极上的金属硅化物层的第一厚度的第二厚度。 所得N型和P型MOS晶体管的栅极结构中的间隔物被去除到不同的厚度，从而最小化栅极结构中的变形，并且还改善栅电极的电特性和热稳定性。