公开(公告)号：US20060097406A1

公开(公告)日：2006-05-11

申请号：US10904431

申请日：2004-11-10

Applicant: Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

Inventor： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。 半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US07026234B2

公开(公告)日：2006-04-11

申请号：US10709940

申请日：2004-06-08

Applicant: Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

Inventor： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC: H01L21/44 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract translation: 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。

公开(公告)号：US20060037363A1

公开(公告)日：2006-02-23

申请号：US11001732

申请日：2004-12-01

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: C03B11/08

CPC classification number: H05B3/84 ,  C03B11/122 ,  C23C14/024 ,  C23C14/0664 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H05B2203/017 ,  Y02P40/57

Abstract: A heat transfer plate for molding glass. The heat transfer plate includes a substrate having an operating surface, an intermediate layer overlying the operating surface of the substrate, and a passivation film overlying the intermediate layer.

Abstract translation: 一种用于成型玻璃的传热板。 传热板包括具有操作表面的基板，覆盖基板的操作表面的中间层以及覆盖中间层的钝化膜。

公开(公告)号：US20060010919A1

公开(公告)日：2006-01-19

申请号：US11176807

申请日：2005-07-06

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: C03B11/06

CPC classification number: C03B11/086 ,  C03B2215/12 ,  C03B2215/24 ,  C03B2215/31 ,  C03B2215/32 ,  C03B2215/38 ,  C23C16/26 ,  C23C28/046

Abstract: A molding core includes: a core body having an article-shaping surface; an intermediate film formed on the article-shaping surface of the core body and including a first composite layer that contains carbon, nitrogen, and at least one bonding-enhancing element which is selected from silicon, titanium, aluminum, tungsten, tantalum, chromium, zirconium, vanadium, niobium, hafnium, and boron, and which forms covalence bonding with the carbon and the nitrogen; and a hard coating that includes a carbon film formed on the intermediate film.

Abstract translation: 成形芯包括：具有制品成形表面的芯体; 形成在芯体的制品成形表面上的中间膜，并且包括含有碳，氮和至少一种选自硅，钛，铝，钨，钽，铬等的粘合增强元素的第一复合层， 锆，钒，铌，铪和硼，并且与碳和氮形成共价键; 以及包含在中间膜上形成的碳膜的硬涂层。

公开(公告)号：US06339025B1

公开(公告)日：2002-01-15

申请号：US09304436

申请日：1999-04-03

Applicant: Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

Inventor： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

IPC: H01L2144

CPC classification number: H01L21/76886 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract translation: 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键，富硅氮化物层中的硅容易与铜反应，并且在铜和富硅氮化物层之间形成铜硅化物层。 因此，可以提高铜和富硅氮化物层的粘合性。

公开(公告)号：US07211500B2

公开(公告)日：2007-05-01

申请号：US10950909

申请日：2004-09-27

Applicant: Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

Inventor： Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/301

CPC classification number: H01L21/78

Abstract: A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

Abstract translation: 描述切割晶片之前的预处理。 晶片包括多个划痕线和由划线限定的多个管芯，并且材料层覆盖晶片。 执行预处理步骤以去除靠近模具的拐角区域的划线上的材料层。 在切割晶片之前在拐角区域去除材料层能够保持切割模具的拐角区域的完整性。

公开(公告)号：US20070056325A1

公开(公告)日：2007-03-15

申请号：US11451458

申请日：2006-06-13

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: C03B11/00

CPC classification number: C03B11/082 ,  C03B33/03 ,  C03B2215/414 ,  Y02P40/57

Abstract: An optical article includes a glass sheet having a top surface, a bottom surface, an array of optical elements formed between the top and bottom surfaces and arranged in rows that intersect each other along two intersecting cutting directions of the glass sheet, and at least two aligning marks formed on one of the top and bottom surfaces and spaced apart from each other in one of the cutting directions. A molding assembly for making the optical article is also disclosed.

Abstract translation: 光学制品包括具有顶表面，底表面，形成在顶表面和底表面之间并沿着玻璃板的两个相交切割方向彼此相交的排布置的玻璃板，以及至少两个 在一个切割方向上形成在顶表面和底表面中的一个上并且彼此间隔开的对准标记。 还公开了一种用于制造光学制品的模制组件。

公开(公告)号：US07170167B2

公开(公告)日：2007-01-30

申请号：US10711536

申请日：2004-09-24

Applicant: Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

Inventor： Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

IPC: H01L23/48

CPC classification number: H01L24/97 ,  H01L23/15 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract translation: 本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。 在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。 晶片通过其上的凸块或焊盘与玻璃基板连接。 在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。 之后，进行分割步骤，并获得多个芯片级封装结构。

公开(公告)号：US07071575B2

公开(公告)日：2006-07-04

申请号：US10904431

申请日：2004-11-10

Applicant: Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

Inventor： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC: H01L23/12 ,  H00L23/48 ,  H00L29/40

CPC classification number: H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。 半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US20060073676A1

公开(公告)日：2006-04-06

申请号：US10950909

申请日：2004-09-27

Applicant: Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

Inventor： Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

IPC: H01L21/78

CPC classification number: H01L21/78

Abstract: A pre-process before cutting a wafer is described. The wafer comprises a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

Abstract translation: 描述切割晶片之前的预处理。 晶片包括多个划痕线和由划线限定的多个管芯，并且材料层覆盖晶片。 执行预处理步骤以去除靠近模具的拐角区域的划线上的材料层。 在切割晶片之前在拐角区域去除材料层能够保持切割模具的拐角区域的完整性。