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    Method for testing semiconductor components using bonded electrical connections
    26.
    发明授权
    Method for testing semiconductor components using bonded electrical connections 有权
    使用接合电连接测试半导体元件的方法

    公开(公告)号：US07271611B2

    公开(公告)日：2007-09-18

    申请号：US11698678

    申请日：2007-01-26

    Applicant: Warren M. Farnworth ,  Mark Tuttle

    Inventor： Warren M. Farnworth ,  Mark Tuttle

    IPC: G01R31/26

    CPC classification number: G01R31/2886

    Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.

    Abstract translation: 用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

    Methods for forming through-wafer interconnects and structures resulting therefrom
    27.
    发明申请
    Methods for forming through-wafer interconnects and structures resulting therefrom 有权
    用于形成贯穿晶片互连和由此产生的结构的方法

    公开(公告)号：US20070048994A1

    公开(公告)日：2007-03-01

    申请号：US11219132

    申请日：2005-09-01

    Applicant: Mark Tuttle

    Inventor： Mark Tuttle

    IPC: H01L21/44

    CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K7/06 ,  H01L2924/014 ,  H01L2224/05552

    Abstract: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

    Abstract translation: 本发明涉及在半导体衬底中形成贯穿晶片互连的方法以及所得到的结构。 在一个实施例中，用于形成贯通晶片互连的方法包括提供在其表面上具有焊盘的衬底，在焊盘和衬底的表面上沉积钝化层，以及通过钝化层和焊盘形成孔 使用基本上连续的过程。 绝缘层沉积在孔中，随后是导电层和导电填料。 在本发明的另一实施例中，形成半导体器件，其包括延伸穿过导电焊盘并与导电焊盘电耦合的第一互连结构，而第二互连结构通过另一个导电焊盘形成，同时与之电绝缘。 还公开了使用该方法制造的半导体器件和组件。

    Method, interconnect and system for testing semiconductor components
    28.
    发明申请
    Method, interconnect and system for testing semiconductor components 有权
    用于测试半导体元件的方法，互连和系统

    公开(公告)号：US20060181298A1

    公开(公告)日：2006-08-17

    申请号：US11057500

    申请日：2005-02-14

    Applicant: Warren Farnworth ,  Mark Tuttle

    Inventor： Warren Farnworth ,  Mark Tuttle

    IPC: G01R31/26

    CPC classification number: G01R31/2886

    Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.

    Abstract translation: 用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

    Integrated circuits with contemporaneously formed array electrodes and logic interconnects
    30.
    发明申请
    Integrated circuits with contemporaneously formed array electrodes and logic interconnects 审中-公开
    具有同时形成的阵列电极和逻辑互连的集成电路

    公开(公告)号：US20060099797A1

    公开(公告)日：2006-05-11

    申请号：US11315731

    申请日：2005-12-22

    Applicant: Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    Inventor： Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    IPC: H01L21/4763 ,  H01L21/336 ,  H01L21/8242

    CPC classification number: H01L27/228 ,  G11C5/06 ,  G11C11/14 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10897

    Abstract: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

    Abstract translation: 本发明涉及用于集成电路存储器件的互连。 本发明的实施例包括以相对较少的步骤制造用于存储器件的互连的工艺。 本发明的实施例还包括具有在芯片的不同区域中具有不等间距尺寸的金属化层的存储器件，从而允许在芯片的不同区域中同时制造阵列电极和电互连。 这减少了用于制造互连的制造步骤的数量，从而加快制造并降低生产成本。

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