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    BEOL structures incorporating active devices and mechanical strength
    21.
    发明授权
    BEOL structures incorporating active devices and mechanical strength 有权
    包含有源器件和机械强度的BEOL结构

    公开(公告)号：US08624323B2

    公开(公告)日：2014-01-07

    申请号：US13149797

    申请日：2011-05-31

    申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

    摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

    摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

    RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS
    27.
    发明申请
    RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS 审中-公开
    作为金属电介质的低K和超低K有机硅膜的疏水性恢复

    公开(公告)号：US20110003402A1

    公开(公告)日：2011-01-06

    申请号：US12749213

    申请日：2010-03-29

    申请人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

    发明人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR′Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R′ are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

    摘要翻译： 通常用于减少集成电路中的RC延迟的是多孔有机硅酸盐的介电膜，其具有二氧化硅像主链与烷基或芳基（以增加材料的疏水性并产生自由体积）直接连接到网络中的Si原子。 Si-R键在暴露于等离子体或通常用于加工的化学处理中很少存活; 这在具有开孔细孔结构的材料中尤其如此。 当Si-R键断裂时，材料由于形成亲水硅烷醇而损失疏水性，并且低介电常数受损。 使用新型甲硅烷基化剂回收材料的疏水性的方法，其可以具有通式（R2N）XSiR'Y，其中X和Y分别为1至3和3至1的整数，并且其中R和 R'选自氢，烷基，芳基，烯丙基和乙烯基部分。 由于甲硅烷基化处理，多孔有机硅酸盐的机械强度也得到改善。

    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES
    28.
    发明申请
    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES 有权
    具有由两个光刻过程产生的三维特征的互连结构

    公开(公告)号：US20090294982A1

    公开(公告)日：2009-12-03

    申请号：US12538114

    申请日：2009-08-08

    申请人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    发明人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    IPC分类号： H01L23/522

    CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

    摘要翻译： 一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。 该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。 该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。 因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

    METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY
    29.
    发明申请
    METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
    用于实现超低K材料和生产的结构的硬掩模自由集成的方法

    公开(公告)号：US20070249156A1

    公开(公告)日：2007-10-25

    申请号：US11672608

    申请日：2007-02-08

    申请人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    发明人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76826 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76883

    摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.

    摘要翻译： 描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法 盖是蚀刻停止层和阻挡层。 在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。 还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。