公开(公告)号：US10163830B2

公开(公告)日：2018-12-25

申请号：US15344893

申请日：2016-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US10163693B1

公开(公告)日：2018-12-25

申请号：US15851304

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/304 ,  H01L21/306 ,  H01L23/28 ,  H01L21/768 ,  H01L21/02 ,  H01L23/29

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US10043688B1

公开(公告)日：2018-08-07

申请号：US15867071

申请日：2018-01-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy E. Minnich ,  Brandon P. Wirz ,  Bret K. Street ,  James M. Derderian

IPC: B32B43/00 ,  H01L21/67 ,  H01L21/683

Abstract: An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to selectively connect the tape to a semiconductor device. The bladder includes one or more chambers that may be selectively expanded to move a portion of the bladder and adhesive layer away from the tape, which may enable the removal of the semiconductor device. The flow of fluid into each of the chambers may selectively expand the chambers. The chambers may have a substantially rounded upper profile or a substantially pointed upper profile. A material within the chambers may be heated to expand the chambers. A plurality of conduits may permit the flow of fluid into the chambers. The conduits may be inserted into the bladder. The chambers may be collapsed after expansion to enable the removal of a semiconductor device from the tape.

公开(公告)号：US20180040592A1

公开(公告)日：2018-02-08

申请号：US15788094

申请日：2017-10-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/075 ,  H01L23/40 ,  H01L23/00 ,  H01L25/04 ,  H01L23/498 ,  H01L23/34 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

公开(公告)号：US20170365584A1

公开(公告)日：2017-12-21

申请号：US15693750

申请日：2017-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/367 ,  H01L23/40 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3738 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2224/83

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US20160013173A1

公开(公告)日：2016-01-14

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Abstract translation: 封装半导体管芯组件的方法。 在一个实施例中，一种方法涉及将具有第一管芯和多个第二管芯的半导体管芯组件封装在第一管芯上，其中第一管芯具有从第二管芯的堆叠体横向向外延伸的周边区域 。 该方法可以包括将热传递结构耦合到第一模具的周边区域并且在第二模具之间流动底部填充材料。 在将热传递结构连接到第一模具的周边区域之后，底部填充材料流动，使得热转印结构限制底部填充材料的横向流动。

公开(公告)号：US11967576B2

公开(公告)日：2024-04-23

申请号：US17370427

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian

IPC: H01L23/00 ,  B23K1/005 ,  B23K101/40 ,  H01L21/268 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/11 ,  B23K1/0056 ,  H01L21/268 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/94 ,  B23K2101/40 ,  H01L2221/68327 ,  H01L2224/117 ,  H01L2224/11849

Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

公开(公告)号：US20210335741A1

公开(公告)日：2021-10-28

申请号：US17370427

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian

IPC: H01L23/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  B23K1/005

Abstract: Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

公开(公告)号：US11139258B2

公开(公告)日：2021-10-05

申请号：US16782298

申请日：2020-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US10580746B2

公开(公告)日：2020-03-03

申请号：US16102960

申请日：2018-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.