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    Arrays Of Elevationally-Extending Strings Of Memory Cells And Methods Used In Forming An Array Of Elevationally-Extending Strings Of Memory Cells
    22.
    发明申请
    Arrays Of Elevationally-Extending Strings Of Memory Cells And Methods Used In Forming An Array Of Elevationally-Extending Strings Of Memory Cells 审中-公开

    公开(公告)号：US20200083059A1

    公开(公告)日：2020-03-12

    申请号：US16128109

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

    IPC: H01L21/311 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/02

    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

    Integrated structures and methods of forming integrated structures
    24.
    发明授权
    Integrated structures and methods of forming integrated structures 有权

    公开(公告)号：US10580792B2

    公开(公告)日：2020-03-03

    申请号：US16107294

    申请日：2018-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

    Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells
    26.
    发明申请
    Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells 审中-公开

    公开(公告)号：US20190267394A1

    公开(公告)日：2019-08-29

    申请号：US16406148

    申请日：2019-05-08

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Luan C. Tran ,  Jie Li ,  Anish A. Khandekar ,  Kunal Shrotri

    IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/792 ,  H01L29/51 ,  H01L29/06 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11556

    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

    DRAM Cells and Methods of Forming Silicon Dioxide
    28.
    发明申请
    DRAM Cells and Methods of Forming Silicon Dioxide 审中-公开
    DRAM电池和形成二氧化硅的方法

    公开(公告)号：US20150279694A1

    公开(公告)日：2015-10-01

    申请号：US14740072

    申请日：2015-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Shivani Srivastava ,  Kunal Shrotri ,  Fawad Ahmed

    IPC: H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78

    CPC classification number: H01L21/324 ,  H01L21/02164 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28211 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

    Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

    Abstract translation: 一些实施方案包括形成二氧化硅的方法，其中使用不大于约1000℃的第一处理温度在硅上形成二氧化硅，并且其中二氧化硅和硅之间的界面利用第二处理温度 其为至少约1050℃。一些实施方案包括形成晶体管的方法，其中形成沟槽以延伸至单晶硅。 利用第一处理温度不大于约1000℃，沿着沟槽内部的多个结晶平面形成二氧化硅，并且利用第二处理温度对二氧化硅和单晶硅之间的界面进行退火 至少约1050℃。晶体管栅极形成在沟槽内，并且在与晶体管栅极相邻的单晶硅内形成一对源/漏区。 一些实施例包括DRAM单元。

    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES
    29.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND RELATED SEMICONDUCTOR DEVICES AND STRUCTURES 有权
    形成半导体器件结构和相关半导体器件和结构的方法

    公开(公告)号：US20140374811A1

    公开(公告)日：2014-12-25

    申请号：US13921509

    申请日：2013-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H01L21/308 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/788

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region.

    Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和在控制区域下具有基本对准侧壁和电荷结构的封盖区域。

    Methods of forming electronic devices using materials removable at different temperatures
    30.
    发明授权
    Methods of forming electronic devices using materials removable at different temperatures 有权

    公开(公告)号：US12069856B2

    公开(公告)日：2024-08-20

    申请号：US18047214

    申请日：2022-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Chandra S. Tiwari ,  Kunal Shrotri

    IPC: H10B41/27 ,  H10B41/10 ,  H10B51/00

    CPC classification number: H10B41/27 ,  H10B51/00 ,  H10B41/10

    Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

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