公开(公告)号：US20140291747A1

公开(公告)日：2014-10-02

申请号：US13852988

申请日：2013-03-28

申请人： Fatma A. Simsek-Ege ,  Krishna K. Parat

发明人： Fatma A. Simsek-Ege ,  Krishna K. Parat

IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/3088 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32134 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4933 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.

摘要翻译： 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 在制造存储器件期间，使用钨硅化物作为蚀刻停止层代替常规使用的氧化铝以形成具有高纵横比的通道柱。 使用钨硅化物可用于消除不期望的蚀刻停止凹部和当通常使用Al氧化物蚀刻停止层时形成的不需要的浮动栅极。

公开(公告)号：US20140169093A1

公开(公告)日：2014-06-19

申请号：US13719558

申请日：2012-12-19

申请人： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

发明人： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C8/12 ,  G11C16/04 ,  G11C16/3409 ,  G11C16/3445

摘要： Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify

摘要翻译： 擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败 验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败

公开(公告)号：US20120261722A1

公开(公告)日：2012-10-18

申请号：US13085083

申请日：2011-04-12

申请人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

发明人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC分类号： H01L23/52 ,  H01L21/82

CPC分类号： H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

摘要翻译： 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US20120137048A1

公开(公告)日：2012-05-31

申请号：US12955765

申请日：2010-11-29

申请人： Hoon Cho ,  Kiran Pangal ,  Krishna K. Parat ,  Neal R. Mielke ,  Pranav Kalavade ,  Iwen Chao

发明人： Hoon Cho ,  Kiran Pangal ,  Krishna K. Parat ,  Neal R. Mielke ,  Pranav Kalavade ,  Iwen Chao

IPC分类号： G06F12/02 ,  G11C16/16 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3495 ,  G11C16/02 ,  G11C16/3404

摘要： A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

摘要翻译： 一种提高闪存耐久性的方法和装置。 在本发明的一个实施例中，高电场被提供给闪速存储器模块的控制门。 施加到闪速存储器模块的高电场消除了控制栅极和闪存模块的有效区域之间的捕获的电荷。 在本发明的一个实施例中，在闪速存储器模块的擦除操作之前，高电场被施加到闪速存储器模块的控制栅极。 通过将高电场施加到闪速存储器模块的控制栅极，本发明的实施例改善了闪存模块的单级或多级单元的编程/擦除循环衰减。

公开(公告)号：US06194784B1

公开(公告)日：2001-02-27

申请号：US08976969

申请日：1997-11-24

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L2348

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生与接触填充物产生的栅极短路的意外扩散接触的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。

公开(公告)号：US5763912A

公开(公告)日：1998-06-09

申请号：US533404

申请日：1995-09-25

申请人： Krishna K. Parat ,  Gregory E. Atwood

发明人： Krishna K. Parat ,  Gregory E. Atwood

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/115

摘要： A switching device having an electrically trimmable threshold voltage comprises a control transistor having favorable programming and erasing characteristics and a sensing transistor suited for stability and high drain voltages. The control transistor includes a floating gate for storing a charge. The control transistor receives an input voltage to vary the charge. The sensing transistor, which has a threshold voltage, includes the floating gate, which is formed from a single, contiguous layer of polysilicon or from separate polysilicon layers connected by metallization, such that the floating gate is shared by the control transistor and the sensing transistor. The control transistor has a tunnel oxide layer between a semiconductor layer and the floating gate having a thickness that is conducive to injection or tunneling of electrons through the tunnel oxide layer. The sensing transistor has a gate oxide layer between the semiconductor layer and the floating gate having a thickness greater than the thickness of the tunnel oxide layer, such as to substantially inhibit injection or tunneling of electrons through the gate oxide layer. Applying the input voltage to the control transistor varies the charge on the floating gate and thereby changes the threshold voltage of the sensing transistor.

摘要翻译： 具有电可调阈值电压的开关装置包括具有良好编程和擦除特性的控制晶体管和适用于稳定性和高漏极电压的感测晶体管。 控制晶体管包括用于存储电荷的浮动栅极。 控制晶体管接收输入电压以改变电荷。 具有阈值电压的感测晶体管包括浮置栅极，该栅极由单个相邻的多晶硅层或由通过金属化连接的单独的多晶硅层形成，使得浮置栅极由控制晶体管和感测晶体管共享 。 控制晶体管具有在半导体层和浮置栅极之间的隧道氧化物层，其厚度有利于电子通过隧道氧化物层的注入或隧穿。 感测晶体管具有在半导体层和浮置栅极之间的栅极氧化层，其厚度大于隧道氧化物层的厚度，例如基本上抑制电子通过栅极氧化物层的注入或隧穿。 将输入电压施加到控制晶体管会改变浮置栅极上的电荷，从而改变感测晶体管的阈值电压。

公开(公告)号：US09754683B2

公开(公告)日：2017-09-05

申请号：US13977011

申请日：2012-03-29

申请人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

发明人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C16/26 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C29/04

CPC分类号： G11C29/50004 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/34 ,  G11C2029/0411 ,  G11C2029/5004

摘要： An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

公开(公告)号：US20150043275A1

公开(公告)日：2015-02-12

申请号：US13963629

申请日：2013-08-09

申请人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

发明人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

摘要： Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例包括用于存储器件的多脉冲编程的技术和配置。 在一个实施例中，一种方法包括应用多个脉冲来对存储器件的一个或多个多电平单元（MLC）进行编程，其中多个脉冲的各个脉冲与一个或多个MLC的各个级别对应，并且在施加多个 脉冲，验证一个或多个MLC的各个级别的编程。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08921891B2

公开(公告)日：2014-12-30

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L21/336

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08705290B2

公开(公告)日：2014-04-22

申请号：US13621052

申请日：2012-09-15

申请人： Prashant S. Damle ,  Krishna K. Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

发明人： Prashant S. Damle ,  Krishna K. Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

IPC分类号： G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.

摘要翻译： 一些实施例包括具有模块和存储器单元的方法和装置。 该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。