公开(公告)号：US6057594A

公开(公告)日：2000-05-02

申请号：US842379

申请日：1997-04-23

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/4334 ,  H01L23/49572 ,  H01L23/49816 ,  H01L2924/0002

摘要： A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.

摘要翻译： 模制的带状球栅阵列封装具有基底结构，其包括导热基底和柔性带，该柔性带从柔性带和基底之间的模制塑料材料的表面上的相对区域延伸。 柔性带具有至少一个导电金属引线图案，其可以被定位在面向基板的带的一侧，并具有多个孔，用于将导电引线图案从带的相对侧暴露以进行焊球接合。 半导体集成电路芯片通过引线将芯片上的接合焊盘互连到金属引线图案，在柔性带的相对区域之间的基板的中心部分上安装。 然后将芯片和引线接合封装在基板上。 该结构是经济的并且允许来自集成电路的高功率耗散。 在制造集成电路封装中的成型工艺是经济的，并且易于使用注塑成型。

公开(公告)号：US5973397A

公开(公告)日：1999-10-26

申请号：US955929

申请日：1997-10-22

申请人： Qwai H. Low ,  Chok J. Chia ,  Seng-Sooi Lim

发明人： Qwai H. Low ,  Chok J. Chia ,  Seng-Sooi Lim

IPC分类号： H01L23/498 ,  H01L23/04

CPC分类号： H01L24/91 ,  H01L23/49811 ,  H01L23/49833 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14

摘要： A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures. Each conductor has a first end connected to a member of the set of bond traces and an opposed second end connected to a corresponding member of a portion of the set of I/O pads. Each of the remaining members of the I/O pads are connected to respective bond traces adjacent to the die cavity by bonding wires. By combining TAB and wire bonding techniques, the number of I/O pads per unit of upper surface area of the integrated circuit may be increased.

摘要翻译： 提出了一种半导体器件和制造方法，其有利地组合TAB和引线键合技术以增加集成电路I / O焊盘密度。 半导体器件包括集成电路，衬底和载体膜（即，TAB带）。 集成电路具有布置在上表面上的一组输入/输出（I / O）焊盘。 衬底在上表面内具有模腔，并且在模腔周围设置一组粘合迹线。 集成电路的下表面附着在模腔内的基板上。 载体膜位于衬底的上表面上，使得集成电路的上表面通过裸片孔露出，并且该组接合迹线的部件的一部分通过一组接合轨迹孔的相应构件暴露 。 每个导体具有连接到该组接合迹线的构件的第一端和连接到该组I / O焊盘的一部分的对应构件的相对的第二端。 I / O焊盘的每个剩余部件通过接合线连接到与模腔相邻的各个焊接迹线。 通过组合TAB和引线键合技术，可以增加集成电路的每单位上表面积的I / O焊盘的数量。

公开(公告)号：US5841191A

公开(公告)日：1998-11-24

申请号：US837530

申请日：1997-04-21

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/50 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107

摘要： A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.

摘要翻译： 一种球栅阵列封装，其中一个或多个导电环与衬底表面上的焊料接合位置一起定位在封装衬底的表面上，以便于引线键合到衬底表面上的集成电路芯片 。 由于可以在芯片和用于配电的导电环之间连接多根导线，所以使用环允许更好地将功率分配到芯片。 这些环形成不同的搁板，用于基板上的电源和接地键，并且通过在环的表面和衬底表面上的接合焊盘之间提供垂直间隔，可以容纳封装中更多的接合。

公开(公告)号：US5814881A

公开(公告)日：1998-09-29

申请号：US770872

申请日：1996-12-20

申请人： Maniam Alagaratnam ,  Qwai H. Low ,  Chok J. Chia

发明人： Maniam Alagaratnam ,  Qwai H. Low ,  Chok J. Chia

IPC分类号： H01L21/98 ,  H01L23/495 ,  H01L23/02

CPC分类号： H01L24/32 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/50 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181

摘要： A single leadframe package having stacked integrated chips mounted therein provides multiple electrical functions. The leadframe package construction includes a leadframe die having a substantially smaller outer peripheral dimension than a first integrated circuit chip mounted face down thereon for supporting from below the first integrated chip without obstructing its bond pads. A second integrated circuit is supported from below in a backside to backside configuration by the first integrated circuit without obstructing the bond pads of the second integrated circuit. A plurality of substantially short conductive wires interconnect electrically the first and second integrated circuit chips with selective ones of a plurality of leadframe conductors. An encapsulating material molds the construction into the single leadframe package.

摘要翻译： 具有安装在其中的堆叠集成芯片的单个引线框封装提供多个电功能。 引线框封装结构包括引线框模具，该引线框模具具有比面向下安装的第一集成电路芯片更小的外周尺寸，用于从第一集成芯片的下方支撑而不阻碍其键合焊盘。 第二集成电路在下面被第一集成电路的背面配置支持，而不会阻碍第二集成电路的接合焊盘。 多个基本上短的导电线将第一和第二集成电路芯片与多个引线框架导体中的选择性导体互连。 封装材料将结构模制成单引线框封装。

公开(公告)号：US5353193A

公开(公告)日：1994-10-04

申请号：US023981

申请日：1993-02-26

申请人： Chok J. Chia ,  Manian Alagaratnam ,  Qwai H. Low ,  Seng-Sooi Lim

发明人： Chok J. Chia ,  Manian Alagaratnam ,  Qwai H. Low ,  Seng-Sooi Lim

IPC分类号： F02F7/00 ,  H01L23/367 ,  H01L23/40 ,  H05K7/20

CPC分类号： H01L23/40 ,  F02F7/00 ,  H01L23/3675 ,  H01L2924/0002 ,  Y10T29/4913

摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.

摘要翻译： 提供了由散热器单元和散热器组成的可拆卸的散热器组件。 散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。 散热器包括附接到与封装的电子设备热接触的内部套环的平台。 该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。 当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。 因此，散热器可以快速方便地附接到散热器或从散热器移除。 因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

公开(公告)号：US08129759B2

公开(公告)日：2012-03-06

申请号：US12625457

申请日：2009-11-24

申请人： Maurice O. Othieno ,  Chok J. Chia ,  Amar J. Amin

发明人： Maurice O. Othieno ,  Chok J. Chia ,  Amar J. Amin

IPC分类号： H01L23/52

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/4943 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括可以具有附接到其上的集成电路管芯的衬底。 该封装包括与用于接地封装的低速电路的地平面电隔离的专用高速接地层。

公开(公告)号：US06670214B1

公开(公告)日：2003-12-30

申请号：US09687263

申请日：2000-10-12

申请人： Chok J. Chia ,  Owai H. Low ,  Ramaswamy Ranganathan

发明人： Chok J. Chia ,  Owai H. Low ,  Ramaswamy Ranganathan

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/8502 ,  H01L2224/85181 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/20753 ,  H01L2924/06 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

摘要翻译： 一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

公开(公告)号：US4868349A

公开(公告)日：1989-09-19

申请号：US191462

申请日：1988-05-09

申请人： Chok J. Chia

发明人： Chok J. Chia

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31 ,  H01L23/433 ,  H01L23/50 ,  H05K1/18 ,  H05K7/20

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  Y10T29/49172

摘要： A molded pin-grid-array package includes a heat sink available at the face opposite to the pins. The heat sink is secured to a printed wiring board that has plated through holes therein that form the desired pin-grip-array and wires are secured in the holes to form the package pins. The heat sink covers an aperture in the board and the semiconductor die is secured to the heat sink inside the cavity thereby formed. After the semiconductor die is attached and the bonding pads connected to the metal traces on the board, the assembly is placed in a transfer mold. Plastic encapsulant is then transfer molded to encapsulate the semiconductor die and to extend flush with the heat sink to form a skirt around the periphery of the board. This leaves the molded package with an available heat sink face for efficient cooling after the package is mounted for ultimate use.

摘要翻译： 模制的针栅阵列封装包括在与引脚相对的表面处可用的散热器。 散热器被固定在印刷电路板上，该印刷电路板在其中镀有通孔，形成所需的针把手阵列，电线固定在孔中以形成封装引脚。 散热器覆盖板中的孔，并且半导体管芯被固定到由此形成的空腔内的散热器。 在安装半导体管芯并且将焊盘连接到板上的金属迹线之后，将组件放置在转移模具中。 然后将塑料密封剂转移模制以封装半导体管芯并且与散热器平齐地延伸以在板的周边形成裙部。 这使得模制包装具有可用的散热器表面，用于在封装安装成最终用途之后进行有效冷却。

公开(公告)号：US06512293B1

公开(公告)日：2003-01-28

申请号：US09875055

申请日：2001-06-05

申请人： Chok J. Chia ,  Seng Sooi Lim ,  Wee K. Liew

发明人： Chok J. Chia ,  Seng Sooi Lim ,  Wee K. Liew

IPC分类号： H01L2304

CPC分类号： H01L23/544 ,  H01L23/49816 ,  H01L25/105 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2225/1005 ,  H01L2924/15162 ,  H05K1/181 ,  H05K2201/10537 ,  H05K2201/10734 ,  Y02P70/611

摘要： A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.

摘要翻译： 公开了一种用于提供由联锁球栅阵列封装形成的球栅阵列组件的方法和装置。 每个球栅阵列封装具有用于机械连接的互锁边缘特征，由此通过互锁边缘特征连接多个球栅阵列封装形成互锁球栅阵列组件。 联锁球栅阵列组件然后可以作为单个单元安装在PC板上。

公开(公告)号：US6114749A

公开(公告)日：2000-09-05

申请号：US884241

申请日：1997-06-27

申请人： Chok J. Chia

发明人： Chok J. Chia

IPC分类号： H01L23/057 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L23/50 ,  H01L23/057 ,  H01L23/49531 ,  H01L23/49558 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181

摘要： An integrated circuit includes a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The package has only a limited number of external connections available for such use. The package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections of the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the package itself.

摘要翻译： 集成电路包括容纳在封装中的半导体集成电路芯片，为电路芯片提供外部电连接。 该包装只有有限数量的外部连接可用于此类使用。 该封装包括内部总线或多个母线，其电连接到电路芯片和选择的封装的外部连接，以提高封装上的外部连接的利用效率，以及改进集成的操作特性 通过改善对芯片的电压和电流分布的电路芯片，并且还在某些情况下消除了与封装本身的外部电连接质量差的后果。