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    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    22.
    发明申请
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 审中-公开

    公开(公告)号：US20170344275A1

    公开(公告)日：2017-11-30

    申请号：US15529970

    申请日：2015-12-18

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Ely TSERN

    IPC: G06F3/06 ,  G06F12/06

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    23.
    发明申请
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 有权

    公开(公告)号：US20250094280A1

    公开(公告)日：2025-03-20

    申请号：US18902067

    申请日：2024-09-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Brent S. HALUKNESS ,  Lawrence LAI

    IPC: G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    LOW LATENCY MEMORY ACCESS
    24.
    发明公开
    LOW LATENCY MEMORY ACCESS 审中-公开

    公开(公告)号：US20230297518A1

    公开(公告)日：2023-09-21

    申请号：US18133700

    申请日：2023-04-12

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE

    IPC: G06F13/16

    CPC classification number: G06F13/1615 ,  G06F13/1689

    Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device’s primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

    MEMORY MODULE REGISTER ACCESS
    25.
    发明申请
    MEMORY MODULE REGISTER ACCESS 有权

    公开(公告)号：US20210303383A1

    公开(公告)日：2021-09-30

    申请号：US17236445

    申请日：2021-04-21

    Applicant: Rambus Inc.

    Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

    IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

    MEMORY MODULE REGISTER ACCESS
    28.
    发明申请
    MEMORY MODULE REGISTER ACCESS 审中-公开

    公开(公告)号：US20190179690A1

    公开(公告)日：2019-06-13

    申请号：US16183470

    申请日：2018-11-07

    Applicant: Rambus Inc.

    Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

    IPC: G06F11/07 ,  G11C29/26 ,  G11C8/12 ,  G11C7/20 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04

    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

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