公开(公告)号：US09880959B2

公开(公告)日：2018-01-30

申请号：US14885173

申请日：2015-10-16

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: H01L23/48 ,  H01L23/60 ,  H01L25/065 ,  G06F13/362 ,  G11C11/408 ,  G11C11/409 ,  H01L23/50 ,  H01L23/00 ,  G06F13/40 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L27/02

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/0018 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H01L23/481 ,  H01L23/50 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance.

公开(公告)号：US20170330610A1

公开(公告)日：2017-11-16

申请号：US15483817

申请日：2017-04-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C5/04 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US09818470B2

公开(公告)日：2017-11-14

申请号：US15098269

申请日：2016-04-13

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20170287571A1

公开(公告)日：2017-10-05

申请号：US15506621

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C11/401 ,  G11C29/02 ,  G11C5/04 ,  G11C29/52 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20170194036A1

公开(公告)日：2017-07-06

申请号：US15391744

申请日：2016-12-27

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: G11C5/14 ,  G06F11/07

CPC classification number: G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US20160293239A1

公开(公告)日：2016-10-06

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G11C8/08 ,  G11C29/44 ,  G06F11/07 ,  G11C8/06

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract translation: 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。

公开(公告)号：US20160086923A1

公开(公告)日：2016-03-24

申请号：US14885173

申请日：2015-10-16

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: H01L25/065 ,  H01L23/00 ,  G11C11/408 ,  H01L23/60 ,  G11C11/409 ,  H01L23/48 ,  H01L23/50

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/0018 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H01L23/481 ,  H01L23/50 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance.

Abstract translation: 半导体器件系统包括多个层叠的基本相同的半导体器件，每个半导体器件包括第一侧和相对的第二侧。 第一和第二焊盘设置在半导体器件的第一侧，而第三和第四焊盘设置在半导体器件的第二侧。 第一接口电路电耦合到第一焊盘和第三焊盘，而第二接口电路电耦合到第二焊盘和第四焊盘。 第二接口电路与第一接口电路分离并且不同。 多个半导体器件中的至少一个第一半导体器件偏离多个半导体器件中的其它半导体器件，使得第一半导体器件上的第四焊盘与多个半导体器件中相邻的半导体器件上的第一焊盘对准并电连接到第一焊盘 设备。 在一些实施例中，第一焊盘与第一电容相关联，而第二焊盘与小于第一电容的第二电容相关联。

公开(公告)号：US20150332753A1

公开(公告)日：2015-11-19

申请号：US14797057

申请日：2015-07-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4096 ,  G11C11/4093

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

Abstract translation: 公开了一种包括具有第一和第二存储器接口电路的逻辑管芯的存储器。 第一存储器管芯与逻辑管芯堆叠在一起，并且包括第一和第二存储器阵列。 第一存储器阵列耦合到第一存储器接口电路。 第二存储器阵列耦合到第二接口电路。 第二存储器管芯与逻辑管芯和第一存储器管芯堆叠在一起。 第二存储器管芯包括第三和第四存储器阵列。 第三存储器阵列耦合到第一存储器接口电路。 第四存储器阵列耦合到第二存储器接口电路。 访问第一和第三存储器阵列是独立于对第二和第四存储器阵列的访问执行的。

公开(公告)号：US09165639B2

公开(公告)日：2015-10-20

申请号：US14538524

申请日：2014-11-11

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G06F3/00 ,  G11C11/4093 ,  G11C5/04 ,  G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US09087572B2

公开(公告)日：2015-07-21

申请号：US14091213

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C7/00 ,  G11C15/00 ,  G11C13/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。