公开(公告)号：US20180166459A1

公开(公告)日：2018-06-14

申请号：US15879257

申请日：2018-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/67 ,  H01L21/324 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/324 ,  H01L21/67167 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device, includes forming a fin structure on a main surface of semiconductor substrate, the fin structure including a silicon material; forming a first gate electrode over the fin structure via a first insulating film, and forming a second gate electrode over the fin structure via a second insulating film having a charge accumulating part, such that the second gate electrode is disposed along a sidewall of the first gate electrode in a plan view; forming source and drain regions over a surface of the fin structure at both sides of a structure defined by the first and second gate electrodes; performing a first heat treatment to the semiconductor substrate to keep the semiconductor substrate at a first predetermined temperature; and forming a first metal film on the fin structure by sputtering in condition that the semiconductor substrate is at the first predetermined temperature.

公开(公告)号：US20160043118A1

公开(公告)日：2016-02-11

申请号：US14885262

申请日：2015-10-16

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L23/26 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14698 ,  H01L31/0352 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device having good properties. Particularly, the semiconductor device is provided which can improve imaging properties. The semiconductor device (CMOS image sensor) includes a plurality of pixels, each having a photodiode PD for generating a charge by receiving light, and a transfer transistor TX for transferring the charge generated by the photodiode PD. The semiconductor device further includes an active region AcTP with the photodiode, and an active region AcG located on an upper side of the region AcTP in the planar direction and having a contact Pg to which a ground potential is applied. A gettering region GET is disposed in the active region AcG.

公开(公告)号：US20150294898A1

公开(公告)日：2015-10-15

申请号：US14683594

申请日：2015-04-10

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3081 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

Abstract translation: 提供具有改进性能的半导体器件。 半导体器件具有形成在半导体衬底的主表面上的第一绝缘膜和形成在第一绝缘膜上的第二绝缘膜。 半导体器件还具有穿过第二绝缘膜并到达第一绝缘膜的第一开口部分，穿过第一绝缘膜并到达半导体衬底的第二开口部分和形成在半导体衬底中的沟槽部分。 第一开口部分的第一开口宽度和第二开口部分的第二开口宽度大于沟槽部分的沟槽宽度。 沟槽部分由第三绝缘膜封闭，同时在沟槽部分留下一个空间。

公开(公告)号：US20230345734A1

公开(公告)日：2023-10-26

申请号：US18179720

申请日：2023-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki OMORI ,  Tadashi YAMAGUCHI

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: A ferroelectric memory cell includes a paraelectric film formed on a semiconductor substrate and a ferroelectric layer formed on the paraelectric film. The ferroelectric layer includes ferroelectric films and a plurality of grains. The ferroelectric films are made of a material containing a metal oxide and a first element. The plurality of grains are made of a material different from the material forming the ferroelectric films, and are made of a ferroelectric.

公开(公告)号：US20220157832A1

公开(公告)日：2022-05-19

申请号：US17097823

申请日：2020-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/1159

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film, a ferroelectric film, a first seed layer and a control gate electrode. The semiconductor substrate includes a source region and a drain region which are formed on a main surface of the semiconductor substrate. The insulating film is formed on the main surface of the semiconductor substrate such that the insulating film is positioned between the source region and the drain region in a plan view. The ferroelectric film is formed on the insulating film and includes hafnium and oxygen. The first seed layer is formed on the ferroelectric film. The control gate electrode is formed on the ferroelectric film. A material of the first seed layer includes at least one material of the ferroelectric film and at least one material of the first conductive film.

公开(公告)号：US20220102558A1

公开(公告)日：2022-03-31

申请号：US17038784

申请日：2020-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L23/522 ,  H01L29/423 ,  G11C11/22

Abstract: A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.

公开(公告)号：US20210028180A1

公开(公告)日：2021-01-28

申请号：US16911811

申请日：2020-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/1159

Abstract: A first amorphous film including hafnium, oxygen and a first element is formed, and a plurality of grains including a second element which differs from any of hafnium, oxygen and the first element is formed on the first amorphous film. An insulating film including a third element that differs from any of hafnium and the second element is formed over the plurality of grains and the first amorphous film, thereby forming a plurality of grains including the second element and the third element. A second amorphous film including the same materials as those of the first amorphous film is formed on the plurality of grains and the first amorphous film. By performing heat treatment, the first amorphous film and the second amorphous film are crystallized to form a first ferroelectric film which is an orthorhombic and a second ferroelectric film which is an orthorhombic, respectively.

公开(公告)号：US20190355584A1

公开(公告)日：2019-11-21

申请号：US16409358

申请日：2019-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/28 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L27/1159

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

公开(公告)号：US20180337055A1

公开(公告)日：2018-11-22

申请号：US15909980

申请日：2018-03-01

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11568 ,  H01L21/02

CPC classification number: H01L29/40111 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/02345 ,  H01L21/02356 ,  H01L21/3105 ,  H01L27/11507 ,  H01L27/11568 ,  H01L27/1159 ,  H01L28/40 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

公开(公告)号：US20180061849A1

公开(公告)日：2018-03-01

申请号：US15602448

申请日：2017-05-23

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/45 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/785

Abstract: Performance and reliability of a semiconductor device are improved. An insulating film is formed such that a control gate electrode, a memory gate electrode, and a gate electrode are embedded, and then tops of the control gate electrode, the memory gate electrode, and the gate electrode are exposed by first polishing. Subsequently, a trench is formed by removing the gate electrode and filled with a metal film, and second polishing is performed to form a gate electrode including the metal film. The insulating film is an O3-TEOS film having a high gap filling characteristic, and thus reduces formation of a seam in the insulating film. Furthermore, the O3-TEOS film is subjected to heat treatment in an oxidizing atmosphere before the first polishing, thereby dishing of the insulating film is reduced during the second polishing.