公开(公告)号：US20160181147A1

公开(公告)日：2016-06-23

申请号：US15054696

申请日：2016-02-26

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

公开(公告)号：US20240178222A1

公开(公告)日：2024-05-30

申请号：US18483737

申请日：2023-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito SUZUMURA ,  Eiji TSUKUDA ,  Yoshiki YAMAMOTO

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/36

CPC classification number: H01L27/0629 ,  H01L29/04 ,  H01L29/36 ,  H01L29/665

Abstract: A resistance element is comprised of a first semiconductor layer of an SOI substrate and a second semiconductor layer formed on the first semiconductor layer. The second semiconductor layer has first and second semiconductor portions spaced apart from each other. The first semiconductor layer has a first region on which the first semiconductor portion is formed, a second region on which the second semiconductor portion is formed, and a third region on which no epitaxial semiconductor layer is formed. Each of the first region and the second region further has a low concentration region located next to the third region. An impurity concentration of the low concentration region is lower than an impurity concentration of the third region. Each semiconductor portion has a middle concentration region located on the low concentration region. An impurity concentration of the middle concentration region is higher than that of the low concentration region.

公开(公告)号：US20230282647A1

公开(公告)日：2023-09-07

申请号：US18317500

申请日：2023-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L27/1207 ,  H01L21/823418

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20190123182A1

公开(公告)日：2019-04-25

申请号：US16100908

申请日：2018-08-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11563

CPC classification number: H01L29/66833 ,  H01L21/0214 ,  H01L21/28017 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/0617 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/792

Abstract: The reliability of a semiconductor device is improved. A first insulating film and a protective film are formed on a semiconductor substrate. The first insulating film and the protective film of a first region are selectively removed, and an insulating film is formed on the exposed semiconductor substrate. In a state where the first insulating film in a second region, a third region, and a fourth region is covered with the protective film, the semiconductor substrate is heat-treated in an atmosphere containing nitrogen, thereby introducing nitrogen to the interface between the semiconductor substrate and the second insulating film in the first region. In other words, a nitrogen introduction point is formed on the interface between the semiconductor substrate and the second insulating film. In this configuration, the protective film acts as an anti-nitriding film.

公开(公告)号：US20190043949A1

公开(公告)日：2019-02-07

申请号：US16150323

申请日：2018-10-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180219067A1

公开(公告)日：2018-08-02

申请号：US15925850

申请日：2018-03-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/74 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180219016A1

公开(公告)日：2018-08-02

申请号：US15936112

申请日：2018-03-26

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/11 ,  H01L29/06 ,  H01L27/12 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0692

Abstract: A semiconductor device, includes: a semiconductor substrate having a first well region; an insulating layer formed on a first portion of the semiconductor substrate, and contacted with the first well region; a semiconductor layer formed on the insulating layer; an element isolation region reaching to an inside of the first well region, in cross-section view; a first gate electrode layer formed on a first portion of the semiconductor layer via a first gate insulating film; a second gate electrode layer formed on a second portion of the semiconductor layer via a second gate insulating film, and formed on a first portion of the element isolation region; an interlayer insulating film covering the first gate electrode layer, the second gate electrode layer and a second portion of the element isolation region; and a first plug conductor layer formed in the interlayer insulating film.

公开(公告)号：US20170263328A1

公开(公告)日：2017-09-14

申请号：US15382646

申请日：2016-12-17

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA ,  Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Yoshiki YAMAMOTO

IPC: G11C17/18 ,  H01L29/36 ,  G11C17/16 ,  H01L21/283 ,  H01L21/768 ,  H01L21/266 ,  H01L27/12 ,  H01L21/84

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L21/266 ,  H01L21/283 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/36

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

公开(公告)号：US20170018611A1

公开(公告)日：2017-01-19

申请号：US15279565

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US20160013287A1

公开(公告)日：2016-01-14

申请号：US14795839

申请日：2015-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO

IPC: H01L29/49 ,  H01L21/283 ,  H01L29/06 ,  H01L29/51 ,  H01L27/12 ,  H01L21/84 ,  H01L21/285

CPC classification number: H01L29/4933 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0607 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78654

Abstract: While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.

Abstract translation: 在增加构成CMOS的MOSFET的阈值电压的同时，通过抑制阈值电压的过度增加来实现元件的省电，并且抑制元件之间的性能变化的发生。 NMOS的栅电极由P型半导体膜构成，在NMOS的栅绝缘膜上设置有高电容率膜，防止了杂质被导入NMOS的沟道区域。 此外，在PMOS的栅极绝缘膜中也设置有高介电常数的膜。