公开(公告)号：US20080295041A1

公开(公告)日：2008-11-27

申请号：US11753644

申请日：2007-05-25

Applicant: Tingdong Zhou ,  Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly

Inventor： Tingdong Zhou ,  Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: H05K1/0262 ,  G06F17/5068 ,  G06F2217/78 ,  H05K3/0005 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane.

Abstract translation: 一种用于电子电路电源平面设计的方法包括分析电子电路的电源平面的直流（DC）特性。 该方法包括基于电力平面的DC特性和PNI特性来分析功率平面的功率网络电感（PNI）特性和识别具有预定电流密度特性的功率平面的受害区域。 该方法还包括用地（GND）形状替换所识别的受害区域，以形成修改后的电力平面。

公开(公告)号：US07430800B2

公开(公告)日：2008-10-07

申请号：US11146441

申请日：2005-06-06

Applicant: Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract translation: 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US08624297B2

公开(公告)日：2014-01-07

申请号：US12579517

申请日：2009-10-15

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L27/10 ,  H01L21/4763

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US08619432B2

公开(公告)日：2013-12-31

申请号：US12895251

申请日：2010-09-30

Applicant: Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

Inventor： Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

IPC: H01R9/00

CPC classification number: H05K3/4623 ,  H05K1/0216 ,  H05K1/141 ,  H05K3/368 ,  H05K2201/10189 ,  Y10T29/49126 ,  Y10T29/49162 ,  Y10T29/53004

Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.

Abstract translation: 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。

公开(公告)号：US08514583B2

公开(公告)日：2013-08-20

申请号：US12945111

申请日：2010-11-12

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H05K7/02

CPC classification number: H05K7/1061 ,  G06F1/183 ,  H01L2924/15311

Abstract: A processor module socket accommodates processor modules of different sizes with adapters that align smaller-sized modules so that module pins align with desired contact points. The largest supported processor module engages with the socket in a conventional manner without the use of an adapter. Smaller processor modules engage within an adapter that in turn engages in the socket in a manner similar to the largest supported processor module. The contact points of the socket support different sized processor modules by keying logical functions based upon the type of processor module installed in the socket.

Abstract translation: 处理器模块插座可容纳具有不同尺寸的处理器模块，适配器可对准较小尺寸的模块，使模块引脚与所需的接触点对准。 最大的支持的处理器模块以常规方式与插座接合，而不使用适配器。 较小的处理器模块接合在适配器中，该适配器又以类似于最大支持的处理器模块的方式进入插座。 插座的接点通过根据安装在插座中的处理器模块的类型键入逻辑功能来支持不同大小的处理器模块。

公开(公告)号：US20120081859A1

公开(公告)日：2012-04-05

申请号：US12895623

申请日：2010-09-30

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

IPC: H05K1/14

CPC classification number: H05K1/112 ,  H05K1/0263 ,  H05K1/0296 ,  H05K1/115 ,  H05K3/3436 ,  H05K2201/0355 ,  H05K2201/1028 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supping power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

Abstract translation: 可以根据各种技术向电子模块供电。 在一般的实施方案中，例如，用于对电子模块的电力的系统可以包括印刷电路板，电子模块和导电箔。 板可以包括在第一侧上的多个接触位置，其中至少一个接触位置电耦合到通孔到板的第二侧。 电子模块可以电耦合到板的第一侧上的接触位置，并且通过电耦合到通孔的至少一个接触位置接收电力。 箔可以适于传送用于电子模块的电力并且电耦合到电路板的第二侧上至少通过电气耦合到接收用于电子模块的电力的接触位置的通孔。

公开(公告)号：US07987399B2

公开(公告)日：2011-07-26

申请号：US11758708

申请日：2007-06-06

Applicant: Richard Dono ,  Roger D. Weekly

Inventor： Richard Dono ,  Roger D. Weekly

IPC: G01R31/28

CPC classification number: G01R31/318533

Abstract: A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

Abstract translation: 用于产品开发的测试卡系统包括被测设备（DUT）。 DUT包括：安装平面; 耦合到所述安装平面的电力输入端口; 耦合到安装平面的JTAG输入端口; 耦合到JTAG输入端口的时钟信号分配网络; 耦合到时钟信号分配网络和电力输入端口的多个锁存器; 以及耦合到所述多个锁存器的输出端口。 测试卡（TC）耦合到DUT，包括：耦合到DUT JTAG输入端口并被配置为向DUT提供测试数据的JTAG接口; 时钟模块，其耦合到所述DUT时钟信号分配网络并且被配置为生成时钟信号; 以及耦合到DUT输出端口并被配置为从DUT接收数据的分析模块。

公开(公告)号：US07920978B2

公开(公告)日：2011-04-05

申请号：US12262021

申请日：2008-10-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F1/26 ,  G06F11/30

CPC classification number: G06F1/305

Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。 将经过时间平均的第一电压与第二电压进行比较。 生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

公开(公告)号：US07917328B2

公开(公告)日：2011-03-29

申请号：US12194606

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

IPC: G06F19/00

CPC classification number: G06F11/3058

Abstract: Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.

Abstract translation: 提供了组装过程中组装体验的温度偏移。 确定组件是否已经超出预定寿命目标的使用。 响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。 计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。 将累积的绩效值与累积压力的绩效预算进行比较。 响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

公开(公告)号：US07765504B2

公开(公告)日：2010-07-27

申请号：US11829179

申请日：2007-07-27

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

Abstract translation: 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。