公开(公告)号：US20180277517A1

公开(公告)日：2018-09-27

申请号：US15718535

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeshik Kim ,  Gwanhyeob Koh

IPC: H01L25/065 ,  H01L43/08 ,  H01L27/22 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L25/50 ,  H01L27/228 ,  H01L43/08 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/80 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L21/76898

Abstract: A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.

公开(公告)号：US11665910B2

公开(公告)日：2023-05-30

申请号：US17546107

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H10B61/00 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US20220102426A1

公开(公告)日：2022-03-31

申请号：US17546107

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/10 ,  H01L43/02

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US11211425B2

公开(公告)日：2021-12-28

申请号：US16895602

申请日：2020-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/10 ,  H01L43/02

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US20210242396A1

公开(公告)日：2021-08-05

申请号：US17083943

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae Kim ,  Kuhoon Chung ,  Gwanhyeob Koh ,  Bae-Seong Kwon ,  Kyungtae Nam

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

公开(公告)号：US10580469B2

公开(公告)日：2020-03-03

申请号：US16460284

申请日：2019-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  G11C5/02 ,  G11C14/00 ,  H01L27/108 ,  H01L45/00 ,  H01L27/24 ,  H01L49/02 ,  H01L23/528

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US20190027482A1

公开(公告)日：2019-01-24

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  Bong-soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24

CPC classification number: H01L27/10897 ,  G11C11/005 ,  G11C14/0045 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US20180358408A1

公开(公告)日：2018-12-13

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: H01L27/22 ,  G11C5/02 ,  G11C11/16 ,  H01L27/24 ,  H01L49/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C5/025 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/224 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/20 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

公开(公告)号：US11659719B2

公开(公告)日：2023-05-23

申请号：US17381768

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/00 ,  H01L27/22 ,  G11C11/02 ,  G11C11/56

CPC classification number: H01L27/228 ,  G11C11/02 ,  G11C11/5614

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

公开(公告)号：US11121175B2

公开(公告)日：2021-09-14

申请号：US16848010

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: G11C11/00 ,  H01L27/22 ,  G11C11/02 ,  G11C11/56

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.