公开(公告)号：US20200168619A1

公开(公告)日：2020-05-28

申请号：US16200115

申请日：2018-11-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20200051993A1

公开(公告)日：2020-02-13

申请号：US16142752

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US20190148392A1

公开(公告)日：2019-05-16

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro KANNO ,  Senaka Krishna KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20160284730A1

公开(公告)日：2016-09-29

申请号：US15179318

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sateesh KOKA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Yao-Sheng LEE ,  George MATAMIS

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

公开(公告)号：US20240237344A1

公开(公告)日：2024-07-11

申请号：US18355745

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Sarath PUTHENTHERMADAM ,  Jiahui YUAN ,  Raghuveer S. MAKALA ,  Longju LIU ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel; and a neighboring electrically conductive layer interference reduction feature provided for a first subset of the electrically conductive layers, such that a second subset of the electrically conductive layers lacks the neighboring electrically conductive layer interference reduction feature.

公开(公告)号：US20240064992A1

公开(公告)日：2024-02-22

申请号：US17821012

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Kartik SONDHI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20240008281A1

公开(公告)日：2024-01-04

申请号：US17809758

申请日：2022-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

公开(公告)号：US20230246084A1

公开(公告)日：2023-08-03

申请号：US17587470

申请日：2022-01-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Koichi MATSUNO

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

公开(公告)号：US20230232634A1

公开(公告)日：2023-07-20

申请号：US17578199

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L23/48

CPC classification number: H01L27/11597 ,  H01L29/78391 ,  H01L29/6684 ,  H01L29/2003 ,  H01L23/481

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US20230231029A1

公开(公告)日：2023-07-20

申请号：US17578177

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L29/51 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L27/1159 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/6684

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.