公开(公告)号：US09406533B2

公开(公告)日：2016-08-02

申请号：US13929776

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  KyungMoon Kim

IPC: H01L21/44 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.

Abstract translation: 形成用于半导体器件和封装的导电和绝缘层的方法。 衬底上装有集成电路器件和互连结构，其中互连结构与集成电路器件相邻。 集成电路器件和互连结构的部分可以覆盖暴露一部分互连结构的封装。 导电材料通过沉积过程形成在互连结构的暴露部分上，然后进行加热过程以改变导电材料的化学性质。 任选地，可以并入分散过程。

公开(公告)号：US09362161B2

公开(公告)日：2016-06-07

申请号：US14220336

申请日：2014-03-20

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/153 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2224/08

Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.

Abstract translation: 半导体器件具有多个半导体管芯。 衬底设置有设置在衬底上的凸起。 第一预制绝缘膜设置在半导体管芯和衬底之间。 在半导体管芯和第一预制绝缘膜上形成互连结构。 凸块包括封装在镀铜中的铜芯。 第一预制绝缘膜包括玻璃布，玻璃纤维或玻璃填料。 衬底包括形成在衬底中并耦合到凸块的导电层。 半导体管芯设置在衬底的凸块之间。 凸块和半导体管芯嵌入在第一预制绝缘膜内。 去除第一预制绝缘膜的一部分以暴露凸块。 凸块将基板电连接到互连结构。

公开(公告)号：US20150004748A1

公开(公告)日：2015-01-01

申请号：US13929775

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： HanGil Shin ,  HeeJo Chi ,  NamJu Cho

IPC: H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4867 ,  H01L21/561 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/4917 ,  H01L2224/49173 ,  H01L2224/49176 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H05K1/092 ,  H05K3/125 ,  H05K3/1283 ,  H05K3/4685 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2203/095 ,  H05K2203/1194 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.

Abstract translation: 形成用于半导体器件和封装的导电跳线迹线的方法。 衬底具有形成在其上的第一，第二和第三迹线，其中第一迹线位于第二和第三迹线之间。 第一条痕迹线可以用覆盖层隔离。 可以通过沉积工艺在第二和第三迹线之间和第一迹线上形成导电层，随后进行加热处理以改变导电层的化学性质。 所得到的导电层能够符合覆盖层并且用于在第二和第三迹线之间提供电连接。