公开(公告)号：US09978833B2

公开(公告)日：2018-05-22

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US20180114727A1

公开(公告)日：2018-04-26

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US09871139B2

公开(公告)日：2018-01-16

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20160111337A1

公开(公告)日：2016-04-21

申请号：US14887484

申请日：2015-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

Abstract translation: 示例性实施例提供制造双轴应变纳米片。 示例性实施例的方面包括：生长具有一个或多个周期的外延晶体初始超晶格，每个周期包括至少三个层，活性材料层，第一牺牲材料层和第二牺牲材料层，第一和第二 具有不同材料特性的牺牲材料层; 在一个或多个周期的每一个中，将每个活性材料层放置在第一和第二牺牲材料层之间，其中第一和第二牺牲材料层的晶格常数不同于活性材料层并且在活性物质层中施加双轴应力 材料层; 选择性地蚀刻掉所有的第一牺牲材料层，从而暴露活性材料的一个表面以进行附加处理，同时活性材料层中的双轴应变由第二牺牲材料层保持; 并且选择性地蚀刻掉所有第二牺牲材料层，从而暴露活性材料层的第二表面用于额外的处理。

公开(公告)号：US20150108584A1

公开(公告)日：2015-04-23

申请号：US14582429

申请日：2014-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.

Abstract translation: 半导体器件包括限定第一有源区的第一器件隔离图案，限定第二有源区的第二器件隔离图案，设置在第一有源区上的第一栅极，第一栅极包括第一厚度的栅极绝缘图案和 第二栅极，其设置在第二有源区上，第二栅极包括具有大于第一厚度的第二厚度的栅极绝缘图案。 第一器件隔离图案的顶表面朝向第一有源区域向下弯曲，使得第一有源区域具有从顶表面和圆角突出的上部。

公开(公告)号：US11556768B2

公开(公告)日：2023-01-17

申请号：US16849638

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G06N3/063 ,  G06N3/02

Abstract: A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.

公开(公告)号：US11552067B2

公开(公告)日：2023-01-10

申请号：US16853535

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L27/02 ,  G06F30/392

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US11461620B2

公开(公告)日：2022-10-04

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US11182686B2

公开(公告)日：2021-11-23

申请号：US16448842

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C11/16 ,  G11C13/00 ,  G11C11/22 ,  G06N5/04 ,  G06F17/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

公开(公告)号：US10985103B2

公开(公告)日：2021-04-20

申请号：US16577591

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Rwik Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.