公开(公告)号：US10090023B2

公开(公告)日：2018-10-02

申请号：US14479707

申请日：2014-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Kiyoshi Kato

IPC: G11C5/14 ,  H01L27/12 ,  G11C11/403

Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.

公开(公告)号：US09978757B2

公开(公告)日：2018-05-22

申请号：US14837177

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/115 ,  H01L23/528 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11517 ,  H01L27/12 ,  H01L49/02 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L27/105 ,  H01L21/108 ,  G11C16/04 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

公开(公告)号：US09818750B2

公开(公告)日：2017-11-14

申请号：US15383274

申请日：2016-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki Ohshima ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: G11C5/06 ,  H01L27/105 ,  H01L27/12 ,  H01L27/11 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  G11C5/14 ,  G06F1/32 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C5/06 ,  G11C5/14 ,  G11C7/04 ,  G11C11/401 ,  G11C11/4074 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/1225 ,  H01L29/7851 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

公开(公告)号：US09793276B2

公开(公告)日：2017-10-17

申请号：US14935607

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Shuhei Nagatsuka ,  Hiroki Inoue ,  Takanori Matsuzaki

IPC: H01L27/105 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12

CPC classification number: H01L27/108 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

公开(公告)号：US09685447B2

公开(公告)日：2017-06-20

申请号：US15175190

申请日：2016-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/118 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/1052 ,  G11C11/405 ,  G11C16/0433 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7833 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US09519175B2

公开(公告)日：2016-12-13

申请号：US14849923

申请日：2015-09-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Toshihiko Saito

IPC: G09G3/36 ,  G02F1/1333 ,  G06F3/044 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1345 ,  H01L27/12 ,  H01L27/13 ,  H01L27/32

CPC classification number: G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

Abstract: A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

公开(公告)号：US20160358942A1

公开(公告)日：2016-12-08

申请号：US15239030

申请日：2016-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC: H01L27/12 ,  H01L23/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

公开(公告)号：US09515661B2

公开(公告)日：2016-12-06

申请号：US14705619

申请日：2015-05-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/012 ,  H01L29/24 ,  H01L29/04 ,  H01L27/06 ,  H01L27/12

CPC classification number: H03K19/018521 ,  H01L27/0629 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0013 ,  H03K19/0016

Abstract: A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.

Abstract translation: 提供了具有减小的漏电流的电路。 第一晶体管，第三晶体管和第二晶体管按此顺序电连接，第二晶体管的漏极和第三晶体管的源极彼此电连接并电连接到输出节点。 第一晶体管是p沟道晶体管。 第二和第三晶体管是n沟道晶体管，每个晶体管包括包括氧化物半导体的半导体区域。 第三晶体管用作控制第一晶体管的漏极和电路的输出节点之间的电连接的开关。 在待机模式下，第三晶体管处于断开状态。

公开(公告)号：US09490370B2

公开(公告)日：2016-11-08

申请号：US14873278

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/108 ,  H01L27/11 ,  H01L49/02

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

公开(公告)号：US09461067B2

公开(公告)日：2016-10-04

申请号：US14703384

申请日：2015-05-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L29/78 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L27/11551 ,  G11C16/0466 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

Abstract translation: 目的在于提供具有高集成度的新型结构的半导体装置。 半导体器件包括具有沟道形成区域，与沟道形成区域电连接的源电极和漏电极的半导体层，与沟道形成区域重叠的栅极电极，以及沟道形成区域和沟道形成区域之间的栅极绝缘层 栅电极。 当从平面方向看时，具有沟道形成区域的半导体层的侧表面的一部分和源电极或漏电极的侧表面的一部分基本上对准。