公开(公告)号：US20070155147A1

公开(公告)日：2007-07-05

申请号：US11714195

申请日：2007-03-06

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L21/3205

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract translation: 半导体器件由以下部分构成：由第一导电膜和第二导电膜构成的互连，其从形成在基板上的绝缘膜上的互连下侧依次堆叠; 以及由第一导电膜制成的下部电容电极，形成在下部电容电极上的电介质膜和形成在该电介质膜上的由上述第二导电膜构成的上部电容电极构成的电容器。

公开(公告)号：US07037371B1

公开(公告)日：2006-05-02

申请号：US09856823

申请日：2000-10-03

Applicant: Shin Hashimoto ,  Takenobu Kishida ,  Kyoko Egashira ,  Yoshifumi Hata ,  Toru Nishiwaki ,  Tomoya Tanaka

Inventor： Shin Hashimoto ,  Takenobu Kishida ,  Kyoko Egashira ,  Yoshifumi Hata ,  Toru Nishiwaki ,  Tomoya Tanaka

IPC: H01L21/28

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S148/019 ,  Y10S148/046

Abstract: After distributing a nonmetal element in a region in the vicinity of a surface portion of a semiconductor layer, a metal film is deposited on the semiconductor layer. Next, a semiconductor-metal compound layer is epitaxially grown in the surface portion of the semiconductor layer by causing a reaction between an element included in the semiconductor layer and a metal included in the metal film through annealing carried out on the metal film.

Abstract translation: 在半导体层的表面部分附近的区域中分布非金属元素之后，在半导体层上沉积金属膜。 接下来，通过在金属膜上进行退火，通过在半导体层中包含的元素与包含在金属膜中的金属之间的反应而在半导体层的表面部分中外延生长半导体 - 金属化合物层。

公开(公告)号：US06585560B2

公开(公告)日：2003-07-01

申请号：US09731011

申请日：2000-12-07

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

公开(公告)号：US6005401A

公开(公告)日：1999-12-21

申请号：US837954

申请日：1997-04-14

Applicant: Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

Inventor： Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  G01R31/2867 ,  G01R31/2831

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Abstract translation: 提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。 具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。 在探针片和绝缘基片之间插入弹性部件。 保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

公开(公告)号：US5645628A

公开(公告)日：1997-07-08

申请号：US502175

申请日：1995-07-13

Applicant: Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

Inventor： Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

IPC: C23C18/34 ,  C23C18/40 ,  C23C18/44 ,  C23C18/31

CPC classification number: C23C18/40 ,  C23C18/34 ,  C23C18/44

Abstract: A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.

Abstract translation: 在半导体衬底上形成的绝缘层中形成接触孔和布线槽。 通过使用含有银离子的硝酸银的化学镀浴，在接触孔和布线槽内部和绝缘层上形成银层; 酒石酸作为银离子的还原剂; 乙二胺作为银离子的络合剂; 和作为pH调节剂的四甲基氢氧化铵的金属离子。 然后，通过化学和机械抛光方法去除绝缘层上的银层，使得在每个接触孔和布线槽中形成嵌入的布线。

公开(公告)号：US5455205A

公开(公告)日：1995-10-03

申请号：US34763

申请日：1993-03-19

Applicant: Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

Inventor： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

IPC: H01L21/3105 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L27/10852 ,  H01L21/3105 ,  H01L27/108 ,  H01L27/105 ,  Y10S148/133 ,  Y10S438/978

Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).

Abstract translation: 公开了一种制造半导体存储器件的方法。 在包括开关晶体管的半导体衬底上形成层间绝缘膜。 然后，形成到达开关晶体管的有源区的存储器节点图形。 通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值 平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。 然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。 然后，在BPSG膜上形成铝布线。 利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低 通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

公开(公告)号：US08592289B2

公开(公告)日：2013-11-26

申请号：US13148543

申请日：2010-02-04

Applicant: Shin Hashimoto ,  Katsushi Akita ,  Shinsuke Fujiwara ,  Hideaki Nakahata ,  Kensaku Motoki

Inventor： Shin Hashimoto ,  Katsushi Akita ,  Shinsuke Fujiwara ,  Hideaki Nakahata ,  Kensaku Motoki

IPC: H01L21/20 ,  H01L21/36 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L21/0242 ,  C30B25/18 ,  C30B29/16 ,  C30B29/403 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/16

Abstract: A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 32 having a primary surface 32a of monoclinic gallium oxide, and a laminate structure 33 of Group III nitride. A semiconductor mesa of the laminate structure 33 includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 of a quantum well structure, and a p-type gallium nitride based semiconductor layer 37. The p-type gallium nitride based semiconductor layer 37 includes, for example, a p-type AlGaN electron block layer and a p-type GaN contact layer. The primary surface 32a of the gallium oxide support base 32 is inclined at an angle of not less than 2 degrees and not more than 4 degrees relative to a (100) plane of monoclinic gallium oxide. Owing to this inclination, the gallium nitride based semiconductor epitaxially grown on the primary surface 32a of the gallium oxide support base has a flat surface.

Abstract translation: 提供了一种氮化镓基半导体器件，其包括在氧化镓晶片上设置有平坦c面的氮化镓基半导体膜。 发光二极管LED包括具有单斜氧化镓的主表面32a的氧化镓载体基底32和III族氮化物的叠层结构33。 层压结构33的半导体台面包括低温GaN缓冲层35，n型GaN层37，量子阱结构的有源层39和p型氮化镓基半导体层37. p 型氮化镓系半导体层37例如包括p型AlGaN电子阻挡层和p型GaN接触层。 氧化镓载体基体32的主表面32a相对于单斜晶系氧化镓的（100）面倾斜2度以上4度以下。 由于该倾斜，在氧化镓载体基体的主表面32a上外延生长的氮化镓基半导体具有平坦的表面。

公开(公告)号：US07981817B2

公开(公告)日：2011-07-19

申请号：US12523073

申请日：2007-08-31

Applicant: Koichi Hashimoto ,  Shin Hashimoto ,  Kyoko Egashira

Inventor： Koichi Hashimoto ,  Shin Hashimoto ,  Kyoko Egashira

IPC: H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66719 ,  Y10S438/942 ,  Y10S438/943 ,  Y10S438/945 ,  Y10S438/951

Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在其表面形成有具有第一导电型半导体层的半导体基板， 形成第一掩模以覆盖半导体层的预定区域; 通过将第二导电类型的杂质离子注入到其上形成有第一掩模的半导体层中，形成第二导电类型的阱区; 通过去除第一掩模的一部分来减小第一掩模的厚度; 通过使用光刻法形成覆盖阱区的一部分的第二掩模; 以及通过将具有第一导电类型的杂质离子注入具有减小的厚度的第一掩模的半导体层和形成在其上的第二掩模来形成第一导电类型的源极区域。

公开(公告)号：US20100048004A1

公开(公告)日：2010-02-25

申请号：US12523073

申请日：2007-08-31

Applicant: Koichi Hashimoto ,  Shin Hashimoto ,  Kyoko Egashira

Inventor： Koichi Hashimoto ,  Shin Hashimoto ,  Kyoko Egashira

IPC: H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66719 ,  Y10S438/942 ,  Y10S438/943 ,  Y10S438/945 ,  Y10S438/951

Abstract: A production method for a semiconductor device includes the steps of: (a) providing a semiconductor substrate having a semiconductor layer 2 of a first conductivity type formed on a surface thereof; (b) forming a first mask 30 so as to cover a predetermined region of the semiconductor layer 2; (c) forming a well region 6 of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer 2 having the first mask 30 formed thereon; (d) reducing the thickness t1 of the first mask 30 by removing a portion of the first mask 30; (e) forming a second mask 34 covering a portion of the well region 6 by using photolithography; and (f) forming a source region 8 of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer 2 having the first mask 30′ with the reduced thickness and the second mask 34 formed thereon.

Abstract translation: 半导体器件的制造方法包括以下步骤：（a）提供具有形成在其表面上的第一导电类型的半导体层2的半导体衬底; （b）形成第一掩模30以覆盖半导体层2的预定区域; （c）通过将第二导电类型的杂质离子注入到其上形成有第一掩模30的半导体层2中，形成第二导电类型的阱区6; （d）通过去除第一掩模30的一部分来减小第一掩模30的厚度t1; （e）通过使用光刻法形成覆盖阱区域6的一部分的第二掩模34; 以及（f）通过将具有第一导电类型的杂质离子注入具有减小的厚度的第一掩模30'和形成在其上的第二掩模34的半导体层2中，形成第一导电类型的源极区8。

公开(公告)号：US20080284026A1

公开(公告)日：2008-11-20

申请号：US11984127

申请日：2007-11-14

Applicant: Shin Hashimoto ,  Tadaaki Mimura

Inventor： Shin Hashimoto ,  Tadaaki Mimura

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00014

Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.

Abstract translation: 半导体器件包括形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一金属图案，形成在第一金属图案上的第二绝缘膜，形成在第二绝缘膜上的第二金属图案，以及第三绝缘膜 金属图案形成在第二绝缘膜中并且连接在第一金属图案和第二金属图案之间。 第三金属图案是单一连续结构，构成第三金属图案的金属的主晶体取向轴平行于半导体基板的主表面。