公开(公告)号：US09209244B2

公开(公告)日：2015-12-08

申请号：US13717803

申请日：2012-12-18

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

公开(公告)号：US09111799B2

公开(公告)日：2015-08-18

申请号：US13109230

申请日：2011-05-17

申请人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

发明人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括掺杂有第一导电型掺杂剂的衬底，并且在衬底上并排布置并沿第一方向延伸的多个堆叠结构，每个堆叠结构包括彼此间隔开的栅电极， 堆叠结构，包括一对堆叠结构，其在垂直于第一方向的第二方向上以第一间隔彼此间隔开;以及拾取区域，在所述一对堆叠结构中的衬底中沿第一方向延伸并掺杂 第一导电型掺杂剂。

公开(公告)号：US08945764B2

公开(公告)日：2015-02-03

申请号：US12669243

申请日：2007-07-19

申请人： Chang Bum Ahn ,  Hyang Mok Lee ,  Byungjin Choi ,  Jun Hwan Jang ,  Hyung Ku Yun ,  Sung-Min Hwang ,  Hyun-Chul Jung

发明人： Chang Bum Ahn ,  Hyang Mok Lee ,  Byungjin Choi ,  Jun Hwan Jang ,  Hyung Ku Yun ,  Sung-Min Hwang ,  Hyun-Chul Jung

IPC分类号： H01M2/08 ,  H01M2/10 ,  H01M2/02 ,  H01M2/30

CPC分类号： H01M2/1066 ,  H01M2/0275 ,  H01M2/0287 ,  H01M2/30 ,  H01M2220/30

摘要： Disclosed herein is a battery pack including a battery cell, having an electrode assembly mounted in a pouch-shaped battery case made of a laminate sheet including a metal layer and a resin layer and is sealed by thermal welding, mounted in a pack case, wherein the pack case includes a frame member constructed in a structure in which a receiving part for receiving the battery cell is open, opposite side sealing portions of the battery cell are mounted to the frame member such that the opposite side sealing portions cover the opposite sides of the frame member, and a sheathing film is applied to the outer surface of the frame member, to which the battery cell is mounted.

摘要翻译： 本发明公开了一种电池组件，包括电池单元，其具有安装在由包括金属层和树脂层的层压片制成的袋状电池壳体中的电极组件，并且通过热焊接而被密封安装在包装盒中，其中 该包装盒包括框架构件，该框架构件构造成用于接收电池单元的接收部分开放，电池单元的相对侧密封部分安装在框架构件上，使得相对侧的密封部分覆盖 框架构件和护套膜被施加到安装有电池单元的框架构件的外表面。

公开(公告)号：US08809938B2

公开(公告)日：2014-08-19

申请号：US13229136

申请日：2011-09-09

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/108

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

摘要： Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.

摘要翻译： 提供三维半导体存储器件。 三维半导体存储器件包括顺序层叠在基板上的第一堆叠结构和第二堆叠结构。 第一堆叠结构包括在衬底上交替重复堆叠的第一绝缘图案和第一栅极图案，并且第二堆叠结构包括在第一堆叠结构上交替重复堆叠的第二绝缘图案和第二栅极图案。 多个第一垂直有源图案穿透第一堆叠结构，并且多个第二垂直有源图案穿透第二堆叠结构。 第一垂直有源图案的数量大于第二垂直有效图案的数量。

公开(公告)号：US08663837B2

公开(公告)日：2014-03-04

申请号：US13132767

申请日：2011-03-11

申请人： Kyung-Su Oh ,  Cha-Hun Ku ,  Yong-Su Choi ,  Sung-Jong Kim ,  Jung-Ah Lee ,  Jae-Dong Chang ,  Dong-Myung Kim ,  Jun-Yong Jeong ,  Sung-Min Hwang ,  Do-Gyun Kim ,  Sang-Bong Nam

发明人： Kyung-Su Oh ,  Cha-Hun Ku ,  Yong-Su Choi ,  Sung-Jong Kim ,  Jung-Ah Lee ,  Jae-Dong Chang ,  Dong-Myung Kim ,  Jun-Yong Jeong ,  Sung-Min Hwang ,  Do-Gyun Kim ,  Sang-Bong Nam

IPC分类号： H01M2/08

CPC分类号： H01M2/0413 ,  H01M2/1241 ,  H01M10/425

摘要： A secondary battery includes an electrode assembly in which a cathode plate and an anode plate are arranged with a separator being interposed therebetween, a case in which the electrode assembly is received, a cap assembly capable of sealing an open end of the case, a gasket interposed between the case and the cap assembly, and a leakage prevention portion formed at one surface of the gasket and/or one surface of the cap assembly, which is oriented toward the electrode assembly and contacted with the gasket.

摘要翻译： 二次电池包括电极组件，其中阴极板和阳极板布置有隔着隔板的电极组件，容纳电极组件的壳体，能够密封壳体的开口端的盖组件，垫圈 插入在壳体和盖组件之间，以及形成在垫圈的一个表面和/或盖组件的一个表面上的防漏部分，其朝向电极组件定向并与垫圈接触。

公开(公告)号：US20120208347A1

公开(公告)日：2012-08-16

申请号：US13367792

申请日：2012-02-07

申请人： Sung-Min Hwang ,  Kwangmin Park ,  Woonkyung Lee ,  Jintaek Park ,  Byong-byun Jang ,  Jumi Yun

发明人： Sung-Min Hwang ,  Kwangmin Park ,  Woonkyung Lee ,  Jintaek Park ,  Byong-byun Jang ,  Jumi Yun

IPC分类号： H01L21/762

CPC分类号： H01L21/762 ,  H01L21/76224 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of fabricating a three-dimensional semiconductor device are provided. Methods may include forming a stack structure including first layers and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. An isolation trench may be formed prior to formation of the channel structures.

摘要翻译： 提供制造三维半导体器件的方法。 方法可以包括形成堆叠结构，其包括交替层叠在衬底上的第一层和第二层，图案化堆叠结构以形成至少一个隔离沟槽，形成贯穿堆叠结构并与隔离沟槽间隔开的沟道结构， 在堆叠结构上的互连线将通道结构彼此连接。 可以在形成通道结构之前形成隔离沟槽。

公开(公告)号：US20100279161A1

公开(公告)日：2010-11-04

申请号：US12667484

申请日：2008-07-02

申请人： Kyong Won Kang ,  Hyang Mok Lee ,  Byungjin Choi ,  Eunyoung Goh ,  Sung-Min Hwang ,  OhYoung Hyun ,  Chang bum Ahn ,  Hyun-Chul Jung ,  Wooyong Lee

发明人： Kyong Won Kang ,  Hyang Mok Lee ,  Byungjin Choi ,  Eunyoung Goh ,  Sung-Min Hwang ,  OhYoung Hyun ,  Chang bum Ahn ,  Hyun-Chul Jung ,  Wooyong Lee

IPC分类号： H01M6/10 ,  H01M4/82

CPC分类号： H01M10/0436 ,  H01M6/46 ,  H01M10/0459 ,  H01M10/052 ,  H01M10/0583 ,  Y10T29/49108 ,  Y10T29/49112

摘要： Disclosed herein is a method of locating a plurality of pull cells constructed in a cathode/separator/anode structure, as basic units, on a separator sheet having a continuous length, further locating a unit electrode or a bi-cell on the separator sheet, and winding the pull cells and unit electrode or the bi-cell to continuously manufacture a stacking/folding type electrode assembly constructed in a structure in which anodes are located at the outermost electrodes forming the outside of the electrode assembly, respectively, wherein the method including a step of continuously supplying a cathode sheet, an anode sheet, a first separator sheet, and a second separator sheet, to manufacture the unit cells, successively arranging the unit cells on the second separator sheet from a first stage to an n stage, and winding the unit cells, a step of arranging cathode tabs and anode tabs at the respective stages, while the cathode tabs and the anode tabs are opposite to each other, and arranging electrode tabs having the same polarity between the neighboring stages, while the electrode tabs are opposite to each other, such that the electrode tabs having the same polarity are located all together at predetermined positions of the wound electrode assembly, and a step of supplying electrodes the number of which is odd from two electrode sheets and electrodes the number of which is even from one electrode sheet.

摘要翻译： 本文公开了一种将在阴极/隔板/阳极结构中构造的多个拉电池作为基本单元定位在具有连续长度的隔板上，将单元电极或双电池进一步放置在隔板上的方法， 以及卷绕拉电池和单元电极或双电池以连续地制造堆叠/折叠型电极组件，其分别以阳极位于形成电极组件外部的最外电极的结构中构成，其中包括 连续地供给阴极片，阳极片，第一隔片片和第二隔片片的步骤，制造单位电池，将第一隔离片的单位电池从第一阶段到第n阶段依次排列，以及 卷绕单元电池，在阴极接片和阳极接片彼此相对的同时在相应的阶段布置阴极接头和阳极接头的步骤，并且布置 电极片在相邻台阶之间具有相同的极性，同时电极片彼此相对，使得具有相同极性的电极片全部位于卷绕的电极组件的预定位置处，并且提供电极的步骤 其数量从两个电极片和电极的数量是奇数的，电极的数量甚至是一个电极片。

公开(公告)号：US20060186935A1

公开(公告)日：2006-08-24

申请号：US11338287

申请日：2006-01-24

申请人： Sung-Min Hwang ,  Kye-Hyun Kyung

发明人： Sung-Min Hwang ,  Kye-Hyun Kyung

IPC分类号： H03B1/00

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C7/1045 ,  G11C7/20

摘要： Disclosed herein is a circuit and method for generating a boost element drive signal in a semiconductor memory device with a mode register set signal. The boost element drive signal generation circuit includes a preliminary drive signal generation unit and a level shifter. The preliminary drive signal generation unit generates a preliminary drive signal in response to a group of mode setting signals. The mode setting signal group is provided from a mode register set. The level shifter generates the boost element drive signal in response to the preliminary drive signal. The pull-up voltage of the boost element drive signal is level-shifted relative to a pull-up voltage of the preliminary drive signal. According to the boost element drive signal generation circuit of the present invention, the activation instant of a boost element drive signal is controlled by a mode setting signal group. Therefore, the boost element drive signal is activated after a boost voltage is stabilized. Therefore, in a semiconductor memory device to which the boost element drive signal generation circuit of the present invention is applied, leakage current flowing through a normal inverter that has an input terminal for receiving the output signal of a boost inverter is greatly decreased.

摘要翻译： 这里公开了一种用于在具有模式寄存器设置信号的半导体存储器件中产生升压元件驱动信号的电路和方法。 升压元件驱动信号生成电路包括初步驱动信号生成单元和电平移位器。 初步驱动信号生成单元响应于一组模式设定信号生成初步驱动信号。 模式设定信号组由模式寄存器组提供。 电平转换器响应于初步驱动信号产生升压元件驱动信号。 升压元件驱动信号的上拉电压相对于初步驱动信号的上拉电压进行电平移位。 根据本发明的升压元件驱动信号生成电路，通过模式设定信号组来控制升压元件驱动信号的启动时刻。 因此，升压元件驱动信号在升压稳定后被激活。 因此，在应用了本发明的升压元件驱动信号生成电路的半导体存储器件中，流过具有用于接收升压逆变器的输出信号的输入端子的正常逆变器的漏电流大大降低。

公开(公告)号：US09859296B2

公开(公告)日：2018-01-02

申请号：US15160335

申请日：2016-05-20

申请人： Se-Jun Park ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

发明人： Se-Jun Park ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

IPC分类号： H01L29/792 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

公开(公告)号：US09373400B2

公开(公告)日：2016-06-21

申请号：US14960839

申请日：2015-12-07

申请人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

发明人： Sung-Min Hwang ,  Han-soo Kim ,  Sun-il Shim

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/02

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.