公开(公告)号：US10062656B2

公开(公告)日：2018-08-28

申请号：US15236526

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Wen-Jen Tsai ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Yi-Ming Lin ,  Min-Hui Lin

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80001 ,  H01L2224/80895 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

公开(公告)号：US10043841B1

公开(公告)日：2018-08-07

申请号：US15663985

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Cheng-Hsien Chou ,  Tsung-Wei Huang ,  Min-Hui Lin ,  Yi-Ming Lin

IPC: H01L21/00 ,  H01L27/146 ,  H01L21/02 ,  H01L21/3105

Abstract: A method for forming an image sensor device is provided. The method includes providing a substrate having a front surface and a back surface. The method includes removing a first portion of the substrate to form a first trench. The method includes forming a first isolation structure in the first trench. The first isolation structure has a top surface. The method includes removing a second portion of the first isolation structure and a third portion of the substrate to form a second trench passing through the first isolation structure and extending into the substrate. The method includes forming a second isolation structure in the second trench. The method includes forming a light-sensing region in the substrate. The method includes removing a fourth portion of the substrate to expose a first bottom portion of the second isolation structure and a backside of the light-sensing region.

公开(公告)号：US20170358620A1

公开(公告)日：2017-12-14

申请号：US15180395

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Sheng-Chan Li ,  Zhi-Yang Wang

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.

公开(公告)号：US09728570B2

公开(公告)日：2017-08-08

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US12027554B2

公开(公告)日：2024-07-02

申请号：US17144757

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Wei Yang ,  Sheng-Chan Li ,  Tsun-Kai Tsao ,  Chih-Cheng Shih ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.

公开(公告)号：US11610812B2

公开(公告)日：2023-03-21

申请号：US17038198

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L21/00 ,  H01L21/768 ,  H01L25/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

公开(公告)号：US20220285480A1

公开(公告)日：2022-09-08

申请号：US17361723

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Ru-Liang Lee ,  Ming Chyi Liu ,  Sheng-Chan Li ,  Sheng-Chau Chen

IPC: H01L49/02

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

公开(公告)号：US20220231058A1

公开(公告)日：2022-07-21

申请号：US17327996

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

公开(公告)号：US11387274B2

公开(公告)日：2022-07-12

申请号：US16680043

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Lu ,  Chih-Hui Huang ,  Sheng-Chan Li ,  Jung-Chih Tsao ,  Yao-Hsiang Liang

IPC: H01L27/146 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/3205

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

公开(公告)号：US20210134663A1

公开(公告)日：2021-05-06

申请号：US17038198

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/528 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.