公开(公告)号：US10665473B2

公开(公告)日：2020-05-26

申请号：US15806338

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Arunima Banerjee

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.

公开(公告)号：US10546830B2

公开(公告)日：2020-01-28

申请号：US16403897

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/29 ,  H01L21/78

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and a plurality of wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface adjacent to the first chip and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface adjacent to the second chip and electrically connected to the wiring layers. The chip package structure includes a first molding layer over the first surface and surrounding the first chip, the first conductive bump, and the first conductive pillar.

公开(公告)号：US20190252363A1

公开(公告)日：2019-08-15

申请号：US16396765

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Cheng-Yi Hong ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Shu-Shen Yeh ,  Kuang-Chun Lee

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

公开(公告)号：US20190139784A1

公开(公告)日：2019-05-09

申请号：US15806338

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Arunima Banerjee

IPC: H01L21/48 ,  H01L23/498

Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.

公开(公告)号：US20160118297A1

公开(公告)日：2016-04-28

申请号：US14990310

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Yu-Ting Huang

IPC: H01L21/768 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/56 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI.

Abstract translation: 一种器件包括金属焊盘和包括与金属焊盘的边缘部分重叠的部分的钝化层。 后钝化互连（PPI）包括覆盖钝化层的迹线部分和连接到迹线部分的焊盘部分。 聚合物层包括PPI上的上部，以及延伸到PPI的焊盘部分并被环绕的PPI的插塞部分。

公开(公告)号：US20250087588A1

公开(公告)日：2025-03-13

申请号：US18506739

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Monsen Liu ,  Shuo-Mao Chen ,  Hsien-Wei Chen ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/28 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A method includes forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on and extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.

公开(公告)号：US12170274B2

公开(公告)日：2024-12-17

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L27/01 ,  H01L49/02

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US12125833B2

公开(公告)日：2024-10-22

申请号：US18346319

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19105

Abstract: A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.

公开(公告)号：US20240021441A1

公开(公告)日：2024-01-18

申请号：US18357520

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Lin ,  Yu-Hao Chen ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Jyh Chwen Frank Lee ,  Shuo-Mao Chen

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L21/4882 ,  H01L23/49838 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/24 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/16 ,  H01L24/83 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49822 ,  H01L2224/73253 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/73209

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

公开(公告)号：US11848305B2

公开(公告)日：2023-12-19

申请号：US17688448

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/50

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.