公开(公告)号：US11901455B2

公开(公告)日：2024-02-13

申请号：US17813888

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2221/1063

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US11532516B2

公开(公告)日：2022-12-20

申请号：US17227831

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Tz-Shian Chen ,  Cheng-Jung Sung ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

公开(公告)号：US20220359158A1

公开(公告)日：2022-11-10

申请号：US17869557

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/321 ,  H01L21/311

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US20220238337A1

公开(公告)日：2022-07-28

申请号：US17457709

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yee-Chia Yeo ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L21/263

Abstract: A method includes placing a wafer into a production chamber, providing a heating source to heat the wafer, and projecting a laser beam on the wafer using a laser projector. The method further includes, when the wafer is heated by both of the heating source and the laser beam, performing a process selected from an epitaxy process to grow a semiconductor layer on the wafer, and an etching process to etch the semiconductor layer.

公开(公告)号：US20210272910A1

公开(公告)日：2021-09-02

申请号：US17306784

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun LIU ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US20210265204A1

公开(公告)日：2021-08-26

申请号：US17094700

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/027 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US10553718B2

公开(公告)日：2020-02-04

申请号：US14211382

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chun-Hsiung Lin ,  Huicheng Chang ,  Syun-Ming Jang ,  Chien-Hsun Wang ,  Mao-Lin Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51

Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.

公开(公告)号：US20240413215A1

公开(公告)日：2024-12-12

申请号：US18451986

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Mu-Chieh Chang ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a spacer layer extending into the lateral recesses, trimming the spacer layer to form inner spacers, and performing a treatment process to reduce dielectric constant values of the inner spacers.

公开(公告)号：US20240145596A1

公开(公告)日：2024-05-02

申请号：US18402173

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20240071722A1

公开(公告)日：2024-02-29

申请号：US18504415

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01J37/32027 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/02063 ,  H01L21/0212 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31138 ,  H01L21/321 ,  H01J2237/3341

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.