公开(公告)号：US10424540B2

公开(公告)日：2019-09-24

申请号：US15724058

申请日：2017-10-03

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Po-Han Lee ,  Chia-Ming Cheng ,  Hsin-Yen Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  H01L27/146

Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US09799588B2

公开(公告)日：2017-10-24

申请号：US14341573

申请日：2014-07-25

Applicant: XINTEC INC.

Inventor： Ching-Yu Ni ,  Chia-Ming Cheng ,  Nan-Chun Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/498 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

公开(公告)号：US09018770B2

公开(公告)日：2015-04-28

申请号：US14337011

申请日：2014-07-21

Applicant: Xintec Inc.

Inventor： Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/58 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract translation: 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫，并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。

公开(公告)号：US08803326B2

公开(公告)日：2014-08-12

申请号：US13678507

申请日：2012-11-15

Applicant: Xintec Inc.

Inventor： Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract translation: 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫，并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。

公开(公告)号：US08633091B2

公开(公告)日：2014-01-21

申请号：US13802262

申请日：2013-03-13

Applicant: Xintec Inc.

Inventor： Chia-Lun Tsai ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/30 ,  H01L21/301

CPC classification number: H01L21/78 ,  H01L21/76898 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/023 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

Abstract translation: 芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中 所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

公开(公告)号：US11784134B2

公开(公告)日：2023-10-10

申请号：US17140952

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/66 ,  H01L2223/6605 ,  H01L2223/6677

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

公开(公告)号：US11355659B2

公开(公告)日：2022-06-07

申请号：US17075544

申请日：2020-10-20

Applicant: XINTEC INC.

Inventor： Po-Han Lee ,  Chia-Ming Cheng ,  Wei-Ming Chien

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/02 ,  H01L31/0216

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

公开(公告)号：US10714528B2

公开(公告)日：2020-07-14

申请号：US16178483

申请日：2018-11-01

Applicant: XINTEC INC.

Inventor： Hsin Kuan ,  Shih-Kuang Chen ,  Chin-Ching Huang ,  Chia-Ming Cheng

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.

公开(公告)号：US09887229B2

公开(公告)日：2018-02-06

申请号：US15226327

申请日：2016-08-02

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

公开(公告)号：US09620431B2

公开(公告)日：2017-04-11

申请号：US14619658

申请日：2015-02-11

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Tsang-Yu Liu ,  Chi-Chang Liao ,  Yu-Lung Huang

IPC: H01L29/06 ,  H01L23/31

CPC classification number: H01L23/3185 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2224/03

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.