公开(公告)号：US06381671B1

公开(公告)日：2002-04-30

申请号：US09342240

申请日：1999-06-29

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US06335898B2

公开(公告)日：2002-01-01

申请号：US09808943

申请日：2001-03-16

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C800

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US06314044B1

公开(公告)日：2001-11-06

申请号：US09594840

申请日：2000-06-15

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1运算的算术电路，以对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US6115319A

公开(公告)日：2000-09-05

申请号：US23880

申请日：1998-02-13

申请人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/408 ,  G11C8/18

CPC分类号： G11C11/4085 ,  G11C7/1072 ,  G11C8/08

摘要： A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.

摘要翻译： 提供了一种用于字线选择器的引导电路，用于将与动态存储单元相连的字线设置在对应于与第二电压对应的第一电压和非选择电平的选择电平。 引导电路产生自举电压，该自举电压相对于与存储器单元连接的高电平位线给予基本上等于地址选择MOSFET的阈值电压的差值，并将自举电压馈送到所选择的字线。 引导电路在与预充电动作之前的SDRAM中由命令指定的动作模式对应的定时与时钟信号同步地激活，从而将字线的选择电平从第一电压改变为自举电压。

公开(公告)号：US5506804A

公开(公告)日：1996-04-09

申请号：US159205

申请日：1993-11-30

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5157629A

公开(公告)日：1992-10-20

申请号：US336345

申请日：1989-04-10

申请人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

发明人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

IPC分类号： G11C11/4074 ,  G11C29/50

CPC分类号： G11C29/50016 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.

摘要翻译： 动态RAM设置有多个1-MOSFET存储单元，每个具有存储电容器和耦合到存储电容器的一个电极的开关MOSFET。 每个存储电容器的另一个电极耦合到控制施加到电容器的电压的开关电路。 开关电路又耦合到电压产生电路（其优选地提供1/2Vcc的电压）和被设置为提供预定测试电压的电压供应电路两者。 因此，通过操作开关电路，在动态RAM的正常操作期间可以向存储单元电容器施加1/2Vcc的电压，并且可以在测试操作期间将预定的测试电压施加到存储单元电容器。

公开(公告)号：US4707625A

公开(公告)日：1987-11-17

申请号：US712141

申请日：1985-03-15

申请人： Kazumasa Yanagisawa

发明人： Kazumasa Yanagisawa

IPC分类号： G11C11/407 ,  H03K19/017 ,  H03K4/58 ,  H03K3/013 ,  H03K3/353 ,  H03K17/10

CPC分类号： H03K19/01735

摘要： A circuit is formed with a combination of a CMOS circuit and a bootstrap capacitor connected to an output terminal of the CMOS circuit in order to reduce the power consumption and to obtain, at the output terminal, a high output voltage exceeding a power supply voltage. In order to prevent the discharge of the bootstrap capacitor, a switching element for preventing a reverse biasing state of the MOSFET on the power supply side of the CMOS circuit is connected in series with the MOSFET.

摘要翻译： 电路由CMOS电路和连接到CMOS电路的输出端子的自举电容器的组合形成，以便降低功耗并且在输出端获得超过电源电压的高输出电压。 为了防止自举电容器的放电，用于防止CMOS电路的电源侧的MOSFET的反向偏置状态的开关元件与MOSFET串联连接。

公开(公告)号：US08063691B2

公开(公告)日：2011-11-22

申请号：US13020169

申请日：2011-02-03

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

IPC分类号： H03L5/00

CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。

公开(公告)号：US08031511B2

公开(公告)日：2011-10-04

申请号：US13024252

申请日：2011-02-09

申请人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

发明人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00 ,  G11C7/04

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2213/79

摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。

公开(公告)号：US20110012206A1

公开(公告)日：2011-01-20

申请号：US12891208

申请日：2010-09-27

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC分类号： H01L27/088

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。