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    METHOD AND APPARATUS FOR PROVIDING CANCELLATION OF HARMONICS SIGNALS WITH MODULATED SIGNALS FOR MULTI-CHANNELS
    21.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING CANCELLATION OF HARMONICS SIGNALS WITH MODULATED SIGNALS FOR MULTI-CHANNELS 有权
    用于多通道调制信号提取谐波信号的方法和装置

    公开(公告)号：US20090096514A1

    公开(公告)日：2009-04-16

    申请号：US11872667

    申请日：2007-10-15

    Applicant: Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

    Inventor： Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

    IPC: H04B1/10

    CPC classification number: H04B1/0475

    Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

    Abstract translation: 用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。 示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。 估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。 估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。 参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。 如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。

    Method and system for implementing a baseband compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK
    23.
    发明授权
    Method and system for implementing a baseband compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK 有权
    用于实现用于QPSK和OQPSK的非线性乘法上变频器的基带压缩方案的方法和系统

    公开(公告)号：US07289424B1

    公开(公告)日：2007-10-30

    申请号：US10269741

    申请日：2002-10-11

    Applicant: Roger Stenerson ,  WeiMin Zhang

    Inventor： Roger Stenerson ,  WeiMin Zhang

    IPC: H04J9/00

    CPC classification number: H04L27/2092 ,  H04L27/20

    Abstract: A system for implementing a base band compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK includes a bit combining module, a quadrant remap module, a look-up table (LUT) and a zoom adjust module. The bit combining module is configured to generate an address based on a number of symbols received as input data. Using the address provided by the bit combining module, the quadrant remap module remaps symbols from quadrants “2”, “3” and “4” to quadrant “1” and generates signals to look up corresponding output data from the LUT. The zoom adjust module generates a number of solutions corresponding to the input data using the corresponding output data retrieved from the LUT. The zoom adjust module is then used to select the best output from the solutions to provide a smooth output signal that does not have any discontinuities.

    Abstract translation: 用于实现用于QPSK和OQPSK的非线性乘法上变频器的基带压缩方案的系统包括位组合模块，象限重映射模块，查找表（LUT）和变焦调整模块。 位组合模块被配置为基于作为输入数据接收的符号的数量来生成地址。 使用比特组合模块提供的地址，象限重映射模块将象限“2”，“3”和“4”的符号重新映射到象限“1”，并生成信号以从LUT中查找相应的输出数据。 变焦调整模块使用从LUT检索的相应输出数据生成与输入数据相对应的多个解。 然后，缩放调整模块用于从解决方案中选择最佳输出，以提供没有任何不连续性的平滑输出信号。

    Method and system for providing a high speed multi-stream MPEG processor
    24.
    发明申请
    Method and system for providing a high speed multi-stream MPEG processor 有权
    提供高速多流MPEG处理器的方法和系统

    公开(公告)号：US20050031042A1

    公开(公告)日：2005-02-10

    申请号：US10888551

    申请日：2004-07-09

    Applicant: Weimin Zhang ,  Binfan Liu ,  Zhongqiang Wang

    Inventor： Weimin Zhang ,  Binfan Liu ,  Zhongqiang Wang

    IPC: G06K9/36 ,  H01L20060101 ,  H04N5/00 ,  H04N5/272 ,  H04N7/12 ,  H04N7/26 ,  H04N7/50

    CPC classification number: H04N21/2362 ,  H04N19/174 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N21/40

    Abstract: An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.

    Abstract translation: 提供MPEG处理器。 根据处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。 然后从芯片外存储器中检索通道的相应数据进行处理。 然后对所检索的数据进行解码。 解码结果和相关信息存储在片外存储器中。 可用于解码后续数据的部分或全部相关信息存储在片上存储器中。 当需要显示视频图像时，然后从片外存储器检索所需的相应数据，并将其提供给与模拟显示装置兼容的格式的模拟编码器进行编码。

    Multi-channel broadband content distribution system
    25.
    发明申请
    Multi-channel broadband content distribution system 有权
    多通道宽带内容分发系统

    公开(公告)号：US20030083054A1

    公开(公告)日：2003-05-01

    申请号：US10172777

    申请日：2002-06-14

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Anthony Francesca ,  WeiMin Zhang

    IPC: H04M003/00

    CPC classification number: H04L5/0005 ,  H04L5/0064 ,  H04L5/06 ,  H04L67/32 ,  H04L67/34 ,  H04L69/14 ,  H04N21/23412 ,  H04N21/2365 ,  H04N21/2383 ,  H04N21/2385 ,  H04N21/2402

    Abstract: A system for managing bandwidth in a content distribution system is provided. The system can be incorporated into the content head end of the content distribution system. The system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. How the packets are multiplexed by the program multiplexer into the output queue depends on the specific design and/or application. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal. The frequency block-up converter then takes the analog multi-channel RF signal and shifts its to a higher frequency band for transmission. The shifted analog multi-channel RF signal is then transmitted over a medium to one or more customer premises equipment.

    Abstract translation: 提供了一种用于管理内容分发系统中的带宽的系统。 该系统可以并入到内容分发系统的内容头端。 该系统包括程序多路复用器，多通道调制模块，通道多路复用器，数模转换器和频率块转换器，全部以顺序配置排列。 表示各个内容节目的分组被馈送到节目多路复用器。 程序复用器将数据包复用到输出队列中。 数据包如何被程序多路复用器复用到输出队列中取决于具体的设计和/或应用程序。 然后将来自输出队列的数据包送入多通道调制模块。 多通道调制模块接收分组并将它们路由到表示对应RF信道的各种调制器。 然后，各种调制器调制各个分组以产生对应的RF信号。 然后，这些RF信号被信道多路复用器复用成多信道RF信号。 然后将多通道RF信号转发到数模转换器，以转换成模拟多通道RF信号。 然后，频率块转换器接收模拟多声道RF信号并将其移动到较高频带以进行传输。 然后将移位的模拟多声道RF信号通过介质传送到一个或多个客户驻地设备。

    High throughput interleaver / deinterleaver
    26.
    发明授权
    High throughput interleaver / deinterleaver 失效
    高吞吐量交织器/解交织器

    公开(公告)号：US08352834B2

    公开(公告)日：2013-01-08

    申请号：US12652167

    申请日：2010-01-05

    Applicant: Binfan Liu ,  Junyi Xu

    Inventor： Binfan Liu ,  Junyi Xu

    IPC: G06F11/00 ,  H03M13/00 ,  H04L1/18 ,  G11C29/00

    CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

    Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

    Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

    Method and system for multi-program clock recovery and timestamp correction
    27.
    发明授权
    Method and system for multi-program clock recovery and timestamp correction 失效
    多程序时钟恢复和时间戳校正的方法和系统

    公开(公告)号：US07710965B2

    公开(公告)日：2010-05-04

    申请号：US10996582

    申请日：2004-11-23

    Applicant: Binfan Liu ,  Thomas Ayers ,  Weimin Zhang

    Inventor： Binfan Liu ,  Thomas Ayers ,  Weimin Zhang

    IPC: H04J3/06

    CPC classification number: H04N21/4305 ,  H04N5/4401 ,  H04N21/4307

    Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

    Abstract translation: 解码器包括被配置为接收节目并提取嵌入在节目中的定时信息和时间戳的传输引擎。 加法器被配置为将一组定时偏移量添加到定时信息组，以便从第一时间基准到第二时间基准来调整定时信息。 定时偏移和定时信息的和被称为映射定时信息。 校正引擎被配置为在程序中遇到定时信息时更新定时偏移，并且偏移寄存器被配置为：接收定时偏移，存储定时偏移，并将定时偏移传送给加法器。 加法器还被配置为将时间偏移量添加到时间戳，以便调整从第一时间到第二时间的时间戳的时间基准。 程序是被配置为接收调整的时间戳以解码程序的解码器。

    Method and system for providing jitter-free transmissions for demodulated data stream
    28.
    发明授权
    Method and system for providing jitter-free transmissions for demodulated data stream 有权
    为解调数据流提供无抖动传输的方法和系统

    公开(公告)号：US07424080B1

    公开(公告)日：2008-09-09

    申请号：US10631497

    申请日：2003-07-31

    Applicant: Binfan Liu

    Inventor： Binfan Liu

    IPC: H04L7/00 ,  H03D1/00

    CPC classification number: H04J3/0632 ,  H04N21/4305 ,  H04N21/4382

    Abstract: A system for providing jitter-free transmissions for demodulated data streams is disclosed. In one embodiment, the system includes a demodulator, a packet processor and a timing generator. The demodulator further includes a timing recovery circuit. Output signals from the timing recovery circuit and demodulated output signals from the demodulator are provided to the timing generator. Using these signals, the timing generator then generates an output timing signal. Demodulated data are provided to the packet processor as input. The demodulated data are then output by the packet processor under the control of the output timing signal from the timing generator.

    Abstract translation: 公开了一种用于为解调数据流提供无抖动传输的系统。 在一个实施例中，系统包括解调器，分组处理器和定时发生器。 解调器还包括定时恢复电路。 来自定时恢复电路的输出信号和来自解调器的解调输出信号被提供给定时发生器。 使用这些信号，定时发生器然后产生输出定时信号。 解调的数据作为输入提供给分组处理器。 解调后的数据然后在来自定时发生器的输出定时信号的控制下由分组处理器输出。

    Fully parallel multi-channel demodulator
    29.
    发明授权
    Fully parallel multi-channel demodulator 有权
    全并行多通道解调器

    公开(公告)号：US07388932B1

    公开(公告)日：2008-06-17

    申请号：US10335209

    申请日：2002-12-30

    Applicant: WeiMin Zhang ,  Vladimir Radionov ,  Roger Stenerson ,  Bin-Fan Liu ,  Yu Kou

    Inventor： WeiMin Zhang ,  Vladimir Radionov ,  Roger Stenerson ,  Bin-Fan Liu ,  Yu Kou

    IPC: H03K9/00

    CPC classification number: H04L27/0012 ,  H04L1/004 ,  H04L7/0079 ,  H04L25/03006

    Abstract: An improved multi-channel demodulator is provided. The improved demodulator includes an automatic gain control, a data buffer and a demodulation engine. Data from various RF channels are processed by the automatic gain control in order to keep the data at their respective constant levels. Output from the automatic gain control is passed to the data buffer for storage. Corresponding data from a selected channel is then processed by the demodulation engine. The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing mode, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing. In addition, status and history information relating to the current channel data is stored into a channel status memory and status and history information relating to the next channel to be processed is retrieved from the channel status memory. In one exemplary aspect, in order to reduce the channel switching time, status and history information relating to the next channel to be processed is preloaded during the previous data processing mode. In the waiting mode, the demodulation engine awaits further processing instructions to decide whether to enter into either the data processing mode or the channel switching mode.

    Abstract translation: 提供改进的多通道解调器。 改进的解调器包括自动增益控制，数据缓冲器和解调引擎。 来自各种RF信道的数据由自动增益控制处理，以便将数据保持在它们各自的恒定水平。 自动增益控制的输出传递到数据缓冲区进行存储。 然后由解调引擎处理来自选定信道的对应数据。 改进的解调器能够以三种操作模式中的任一种操作，即数据处理模式，信道切换模式和等待模式。 在数据处理模式中，解调引擎处理当前加载到解调引擎中的信道数据。 在信道切换模式中，解调引擎将当前信道数据存储到数据缓冲器中，并从另一个信道检索和加载信道数据进行处理。 此外，与当前频道数据相关的状态和历史信息被存储到频道状态存储器中，并且从频道状态存储器检索与要处理的下一频道有关的状态和历史信息。 在一个示例性方面，为了减少频道切换时间，在先前的数据处理模式期间预先加载与要处理的下一频道相关的状态和历史信息。 在等待模式中，解调引擎等待进一步的处理指令来决定是进入数据处理模式还是进入信道切换模式。

    Multi-channel broadband content distribution system
    30.
    发明授权
    Multi-channel broadband content distribution system 有权
    多通道宽带内容分发系统

    公开(公告)号：US07353004B2

    公开(公告)日：2008-04-01

    申请号：US10172777

    申请日：2002-06-14

    Applicant: Anthony Francesca ,  WeiMin Zhang

    Inventor： Anthony Francesca ,  WeiMin Zhang

    IPC: H04B1/02 ,  H04B1/66

    CPC classification number: H04L5/0005 ,  H04L5/0064 ,  H04L5/06 ,  H04L67/32 ,  H04L67/34 ,  H04L69/14 ,  H04N21/23412 ,  H04N21/2365 ,  H04N21/2383 ,  H04N21/2385 ,  H04N21/2402

    Abstract: The system of a content head end of a distribution system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal. The frequency block-up converter then takes the analog multi-channel RF signal and shifts its to a higher frequency band for transmission to one or more customer premises equipment.

    Abstract translation: 分配系统的内容头端的系统包括程序多路复用器，多通道调制模块，通道多路复用器，数模转换器和频率块转换器，全部以顺序配置排列。 表示各个内容节目的分组被馈送到节目多路复用器。 程序复用器将数据包复用到输出队列中。 然后将来自输出队列的数据包送入多通道调制模块。 多通道调制模块接收分组并将它们路由到表示对应RF信道的各种调制器。 然后，各种调制器调制各个分组以产生对应的RF信号。 然后，这些RF信号被信道多路复用器复用成多信道RF信号。 然后将多通道RF信号转发到数模转换器，以转换成模拟多通道RF信号。 然后，频率块转换器接收模拟多声道RF信号并将其移动到较高频带以传输到一个或多个客户驻地设备。

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