公开(公告)号：US5714306A

公开(公告)日：1998-02-03

申请号：US428431

申请日：1995-04-25

申请人： Toshiyuki Komatsu ,  Yasue Sato ,  Shin-Ichi Kawate

发明人： Toshiyuki Komatsu ,  Yasue Sato ,  Shin-Ichi Kawate

IPC分类号： C23C16/04 ,  G03F1/68 ,  G03F7/00 ,  G03F7/004 ,  G03F7/20 ,  G03F7/26 ,  G03F7/36 ,  G03F7/38 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/3213

CPC分类号： G03F1/68 ,  C23C16/047 ,  G03F7/2002 ,  G03F7/201 ,  G03F7/2022 ,  G03F7/2043 ,  G03F7/2053 ,  G03F7/265 ,  G03F7/36 ,  G03F7/38 ,  G03F7/7005 ,  G03F7/70841 ,  G03F7/70866 ,  G03F7/70875 ,  G03F7/70991 ,  H01L21/02071 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31662 ,  H01L21/31683 ,  H01L21/32 ,  H01L21/32139 ,  G03F7/00 ,  G03F7/0035 ,  G03F7/0042

摘要： A processing method comprises: a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator; a second step of subjecting the surface of the film deposited in the first step, to irradiation with a beam having a given energy to produce a physical damage on the surface; a third step of subjecting the film surface on which the physical damage is produced in the second step, to selective irradiation with light to partially cause a photochemical reaction so that a mask pattern depending on the desired device structure is formed on the film surface; and a fourth step of carrying out photoetching using as a shielding member the mask pattern formed in the third step.

公开(公告)号：US4295897B1

公开(公告)日：1997-09-09

申请号：US8151379

申请日：1979-10-03

申请人： TEXAS INSTRUMENTS INC

发明人： TUBBS GRAHAM S ,  PONDER JAMES E

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238

CPC分类号： H01L21/76218 ,  H01L21/033 ,  H01L21/265 ,  H01L21/266 ,  H01L21/82 ,  H01L21/8238 ,  Y10S148/082

公开(公告)号：US5420067A

公开(公告)日：1995-05-30

申请号：US123665

申请日：1993-09-20

申请人： David S. Y. Hsu

发明人： David S. Y. Hsu

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76885 ,  Y10S148/104 ,  Y10S438/943 ,  Y10S438/947

摘要： A non-optical method for the formation of sub-half micron holes, vias, or trenches within a substrate. For example, a substrate having at least two buttresses or a trench having a interbuttress distance or a width of 1.0 to 0.5 microns, respectively, is conformally or non-conformally lined with a layer material. Thereafter, the layer material from horizontal surfaces is removed to expose the substrate underneath while leaving the layer material attached to the essentially vertical walls of the buttresses or the trenches essentially intact, thereby, narrowing the interbuttress distance or the trench width, respectively, to sub-half micron dimensions. The exposed substrate surface is then subjected to anisotropic etching to form sub-half micron trenches, holes or vias in the substrate. Finally, the buttresses and layer material are removed from the substrate. Alternatively, a template of buttresses or channel glass having openings, lined with layer material, on the order of sub-half micron widths is placed on a substrate prior to anisotropic etching to form sub-half micron holes, vias or trenches within the substrate. The template is then removed leaving a substrate surface containing sub-half micron trenches, holes or vias. The template structure once made can be used repeatedly.

摘要翻译： 用于在衬底内形成半微米孔，通孔或沟槽的非光学方法。 例如，分别具有至少两个支撑体或具有中间距离或宽度为1.0至0.5微米的沟槽的基底是共形的或非保形地衬有层材料。 此后，去除水平表面的层材料以暴露下面的衬底，同时使附着在支撑体或沟槽的基本上垂直的壁上的层材料基本上完整，从而将衬垫间距离或沟槽宽度分别变窄到子层 - 微米尺寸。 然后将暴露的基板表面进行各向异性蚀刻，以在基板中形成半个半微米的沟槽，孔或通孔。 最后，将支撑体和层材料从基底上除去。 或者，在各向异性蚀刻之前，将具有约半微米宽度的衬层的具有层材料的开口的支撑件或通道玻璃的模板放置在衬底上，以在衬底内形成半个半微米的孔，通孔或沟槽。 然后去除模板，留下含有半微米沟槽，孔或通孔的衬底表面。 一旦制作的模板结构可以重复使用。

公开(公告)号：US5409566A

公开(公告)日：1995-04-25

申请号：US126023

申请日：1993-09-24

申请人： Jeong J. Kim

发明人： Jeong J. Kim

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  B05D5/00

CPC分类号： H01L21/3086 ,  H01L21/033 ,  H01L21/31144 ,  H01L21/32139

摘要： A slope etching process including dipping a pattern forming layer into a predetermined dipping solution containing an etching solution or wet etching and deionized water, so as to utilize a wet etching method only for isotropic etching. There is also provided a slope etching process including forming a photoresist pattern layer having inclined edges and etching the photoresist pattern layer together with the pattern forming layer by using a gas mixture containing an etching gas for dry etching and O.sub.2 gas, so as to utilize a RIE method only for anisotropic etching. According to the processes, it is possible to slope etch the pattern forming layer so as to form a pattern layer having a desired edge slope. Furthermore, the step coverage after process integration and productivity can be improved.

摘要翻译： 一种倾斜蚀刻方法，包括将图案形成层浸渍到含有蚀刻溶液或湿蚀刻和去离子水的预定浸渍溶液中，以便仅利用用于各向同性蚀刻的湿蚀刻方法。 还提供了一种斜面蚀刻工艺，包括通过使用含有用于干蚀刻的蚀刻气体和O 2气体的气体混合物形成具有倾斜边缘的光致抗蚀剂图案层和与图案形成层一起蚀刻光致抗蚀剂图案层，以利用 RIE方法仅用于各向异性蚀刻。 根据这些工艺，可以对图案形成层进行斜率蚀刻，以便形成具有期望边缘斜率的图案层。 此外，可以提高过程集成和生产力之后的步骤覆盖。

公开(公告)号：US5256583A

公开(公告)日：1993-10-26

申请号：US817867

申请日：1992-01-07

申请人： Theodore G. Hollinger

发明人： Theodore G. Hollinger

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L21/70

CPC分类号： H01L21/3065 ,  H01L21/033 ,  H01L21/266 ,  H01L29/41741 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/41766 ,  H01L29/66545

摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

摘要翻译： 多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。 它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。 在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。 使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。 在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。 施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。 在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。 侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。 通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

公开(公告)号：US5119150A

公开(公告)日：1992-06-02

申请号：US664301

申请日：1991-03-04

申请人： Takashi Murakami

发明人： Takashi Murakami

IPC分类号： H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01S5/20

CPC分类号： H01S5/20 ,  H01L21/033 ,  H01L21/2258 ,  H01S5/2059 ,  Y10S148/034 ,  Y10S438/965

摘要： A semiconductor structure includes a compound semiconductor substrate, a compound semiconductor diffusion limiting layer containing aluminum, disposed on the substrate, and having a larger aluminum content than the substrate, a compound semiconductor layer disposed on the diffusion limiting layer, a silicon film disposed on the semiconductor layer, and a diffusion region into which silicon has diffused from the silicon film to reach the interface between the diffusion limiting layer and the substrate. The diffusion limiting layer may be employed in a semiconductor laser to prevent silicon from diffusing beyond desired regions and to form a light-confining structure.

公开(公告)号：US5110760A

公开(公告)日：1992-05-05

申请号：US589758

申请日：1990-09-28

申请人： David S. Y. Hsu

发明人： David S. Y. Hsu

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/76802 ,  H01L21/76807 ,  Y10S148/105 ,  Y10S148/111 ,  Y10S438/947

摘要： Nanometer thick vertical metallic structures are fabricated on a substrate by depositing a metallic layer on a substrate surface on which one or more buttresses are formed, etching the metallic layer to expose the horizontal surfaces of the substrate and the buttresses, and etching the substrate to remove the buttresses, thereby producing vertical structures on the substrate. The metallic layer is formed by thermal decomposition of a volatile metal-containing precursor gas in the presence of a carrier gas at low pressure, unlike that in conventional CVD reactors. The metallic layer thus formed has a grain size which is fraction of the thickness of the vertical structure.

摘要翻译： 通过在其上形成有一个或多个支撑体的衬底表面上沉积金属层，在衬底上制造纳米厚的垂直金属结构，蚀刻金属层以暴露衬底和支撑体的水平表面，并蚀刻衬底以去除 由此在基板上产生垂直结构。 在传统的CVD反应器中，金属层是通过在载气下在低压下的挥发性含金属前体气体的热分解形成的。 如此形成的金属层具有垂直结构厚度分数的粒径。

公开(公告)号：US5064774A

公开(公告)日：1991-11-12

申请号：US632693

申请日：1991-02-19

申请人： Jame R. Pfiester

发明人： Jame R. Pfiester

IPC分类号： H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/033 ,  H01L21/28525 ,  H01L29/66272 ,  Y10S148/01 ,  Y10S148/011

摘要： A fully self-aligned bipolar transistor having low emitter and base-resistances is formed in a semiconductor device. In one embodiment, a patterned masking layer is formed on an active device region of a semiconductor substrate. The patterned masking layer has an opening, within which a TiN sidewall spacer is formed. The active device region is selectively doped to form an intrinsic base, using the TiN sidewall spacer and patterned masking layer as a doping mask. An emitter electrode is formed on the intrinsic base by selective deposition of silicon. An extrinsic base is also formed in the active device region by doping. Self-aligned metal silicide contacts to the extrinsic base and the emitter electrode are formed and the TiN sidewall spacer is removed.

摘要翻译： 在半导体器件中形成具有低发射极和基极电阻的完全自对准双极晶体管。 在一个实施例中，在半导体衬底的有源器件区域上形成图案化掩模层。 图案化掩模层具有开口，在该开口内形成有TiN侧壁间隔物。 有源器件区域被选择性地掺杂以形成本征基极，使用TiN侧壁间隔物和图案化掩模层作为掺杂掩模。 通过选择性沉积硅在本征基底上形成发射电极。 通过掺杂也在有源器件区域中形成非本征基极。 自对准金属硅化物与外部基极接触并形成发射极，并且去除TiN侧壁间隔物。

公开(公告)号：US5047366A

公开(公告)日：1991-09-10

申请号：US264142

申请日：1988-10-28

申请人： Takashi Murakami

发明人： Takashi Murakami

IPC分类号： H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01S5/20

CPC分类号： H01S5/20 ,  H01L21/033 ,  H01L21/2258 ,  H01S5/2059 ,  Y10S148/034 ,  Y10S438/965

摘要： A method of diffusing Si into compound semiconductor from a Si film provided on a surface region of the compound semiconductor, wherein the diffusion is conducted with providing a diffusion stopper layer at a position of predetermined depth from the surface of the compound semiconductor, which stopper layer has a lower diffusion speed than that of the compound semiconductor.A compound semiconductor device includes a compound semiconductor substrate, a diffusion stopper layer provided on the semiconductor substrate, a compound semiconductor layer provided on the diffusion stopper layer, a Si film provided on the semiconductor layer, and Si diffusion regions into which Si is diffused from the Si film so as to reach the interface between the diffusion stopper layer and the semiconductor substrate.

公开(公告)号：US5021354A

公开(公告)日：1991-06-04

申请号：US445241

申请日：1989-12-04

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/28 ,  H01L21/316 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/8238

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/033 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/32155 ,  H01L21/823864 ,  Y10S438/981

摘要： A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type. Sidewall spacers are formed at the edges of the gate electrodes by anisotropically etching a sidewall spacer forming material. Because of the differential thickness of the gate electrode structures, the spacers at the edges of the N-type doped gate electrodes will be of a different thickness than are the sidewall spacers at the edges of the silicon gates not having the N-type doping. The sidewall spacers of different width are, in turn, used as a dopant mask for the formation of doped regions within the surface of the semiconductor substrate. The disclosed process allows independent doping of the polycrystalline silicon and the semiconductor substrate. A high doping concentration in the polycrystalline silicon helps to minimize the diffusing of dopant through a metal silicide layer formed on the polycrystalline silicon.

摘要翻译： 公开了用于制造CMOS器件的工艺，其中选择性地掺杂的硅层被选择性氧化以在硅中和覆盖的氧化硅中提供差分厚度。 根据一个实施例，提供半导体衬底，其具有覆盖该衬底的表面的硅层。 硅层的第一区域选择性地掺杂有N型杂质，而第二区域未被掺杂。 硅被热氧化以形成在N型掺杂区域上的厚度超过未掺杂区域的热氧化物。 相应地，厚热氧化物下的硅的厚度小于薄热氧化物下的硅的厚度。 图案化硅层以形成栅电极和互连，其中一些栅电极由具有N型掺杂剂的硅形成，并且由不掺杂N型的硅形成的一些栅电极。 通过各向异性蚀刻侧壁间隔物形成材料，在栅电极的边缘处形成侧壁间隔物。 由于栅电极结构的差别厚度，N型掺杂栅电极的边缘处的间隔物的厚度与不具有N型掺杂的硅栅极的边缘处的侧壁间隔物的厚度不同。 不同宽度的侧壁间隔物又被用作在半导体衬底的表面内形成掺杂区域的掺杂剂掩模。 所公开的方法允许多晶硅和半导体衬底的独立掺杂。 多晶硅中的高掺杂浓度有助于最小化通过在多晶硅上形成的金属硅化物层的掺杂剂的扩散。