公开(公告)号：US07892939B2

公开(公告)日：2011-02-22

申请号：US12043384

申请日：2008-03-06

申请人： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

发明人： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC分类号： H01L21/76 ,  H01L21/311

CPC分类号： H01L21/76262 ,  H01L21/76278

摘要： The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

摘要翻译： 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US20060273330A1

公开(公告)日：2006-12-07

申请号：US11498774

申请日：2006-08-04

申请人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

IPC分类号： H01L33/00

CPC分类号： H01L27/10894 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

摘要翻译： 一种半导体器件制造方法，包括：选择性地去除SOI衬底中的一部分掩埋氧化物层和第一半导体层，所述SOI衬底具有形成于半导体衬底上方的所述掩埋氧化物层的第一半导体层，并且暴露所述半导体衬底的一部分， 区域，并且在半导体衬底的一部分已经在深度方向上被去除的区域中埋入第二半导体区域。

公开(公告)号：US06768175B1

公开(公告)日：2004-07-27

申请号：US09787877

申请日：2001-03-23

申请人： Takashi Morishita ,  Masahiro Matsui

发明人： Takashi Morishita ,  Masahiro Matsui

IPC分类号： H01L2701

CPC分类号： H01L21/2007 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281

摘要： When a SOI substrate is produced a first silicon layer epitaxially grown on the insulating underlay is ion implanted to make deep part of interface of the silicon layer amorphous, and then annealed to recrystallize. Next, the silicon layer is heat treated to oxidize part of the surface side, and after the silicon oxide is removed by etching, a silicon layer is epitaxially grown on the remaining first silicon layer to form a second silicon layer. Subsequently, the second silicon layer is again ion implanted to make deep part of interface amorphous, then annealing is performed to recrystallize. With this method, a SOI substrate, which is very small in crystal defect density of the silicon layer and good in surface flatness, can be produced. Therefore, on the semiconductor substrate an electronic device or optical device having high device performance and reliability can be realized.

摘要翻译： 当制造SOI衬底时，在绝缘衬底上外延生长的第一硅层被离子注入，以使硅层的界面的深部非晶化，然后退火再结晶。 接下来，对硅层进行热处理以氧化表面侧的一部分，并且在通过蚀刻去除氧化硅之后，在剩余的第一硅层上外延生长硅层以形成第二硅层。 随后，再次离子注入第二硅层，使界面的深部非晶化，然后退火进行重结晶。 通过这种方法，可以制造出硅层的晶体缺陷密度非常小，表面平坦度好的SOI衬底。 因此，可以在半导体基板上实现具有高的器件性能和可靠性的电子器件或光学器件。

公开(公告)号：US06630699B1

公开(公告)日：2003-10-07

申请号：US09653531

申请日：2000-08-31

申请人： Ian Wylie

发明人： Ian Wylie

IPC分类号： H01L2972

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78639

摘要： The present invention provides a transistor device that does not experience the problems associated with the prior art transistor devices. The transistor device includes a dielectric region located in a trench in a semiconductor substrate and a source region and a drain region located in the trench. The source region and drain region are at least partially on the dielectric region. The transistor device further includes a channel region located in the trench between the source region and drain region and at least partially on the dielectric region.

摘要翻译： 本发明提供一种晶体管器件，其不会遇到与现有技术的晶体管器件相关的问题。 晶体管器件包括位于半导体衬底中的沟槽中的介质区域和位于沟槽中的源极区域和漏极区域。 源极区域和漏极区域至少部分地在电介质区域上。 晶体管器件还包括位于源极区域和漏极区域之间的沟槽中并且至少部分地位于电介质区域上的沟道区域。

公开(公告)号：US06555891B1

公开(公告)日：2003-04-29

申请号：US09690674

申请日：2000-10-17

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： H01L2900

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

公开(公告)号：US06409829B1

公开(公告)日：2002-06-25

申请号：US09461609

申请日：1999-12-15

申请人： John Joseph Bastek ,  Thomas J. Krutsick ,  Robert D. Plummer

发明人： John Joseph Bastek ,  Thomas J. Krutsick ,  Robert D. Plummer

IPC分类号： C30B2300

CPC分类号： H01L29/66272 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L27/0207

摘要： Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

摘要翻译： 使用选择性外延生长（SEG）在衬底晶片中形成集成电路器件。 当跨越晶片表面的SEG区域的分布不均匀时，产生不均匀的外延晶片厚度，导致在生长过程中的负载效应。 根据本发明，加载效应被最小化，通过添加无源SEG区域，从而在晶片上产生相对均匀的SEG生长区域分布。 无源区域在成品IC器件中保持未处理。

公开(公告)号：US06180486B2

公开(公告)日：2001-01-30

申请号：US09250895

申请日：1999-02-16

申请人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

发明人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/76278

摘要： A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

摘要翻译： 平面绝缘体上硅（SOI）结构和制造该结构的工艺。 SOI结构具有硅晶片，氧化物层和硅层。 形成从结构的顶表面延伸到硅晶片并且填充有半导体的沟槽。 沟槽有顶部，底部和侧壁。 侧壁具有侧壁硅部分。 沟槽侧壁的侧壁硅部分被沟槽侧壁氧化物层覆盖。 保护侧壁从沟槽顶部到沟槽底部在沟槽侧壁和沟槽侧壁氧化物层上延伸。

公开(公告)号：US5346834A

公开(公告)日：1994-09-13

申请号：US845063

申请日：1992-03-03

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278 ,  Y10S148/014

摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

摘要翻译： 提供了一种用于制造绝缘栅场效应晶体管的改进方法。 作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。 然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。 然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。 然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。 之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。 接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

公开(公告)号：US5308445A

公开(公告)日：1994-05-03

申请号：US957514

申请日：1992-10-05

申请人： Hidemi Takasu

发明人： Hidemi Takasu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76202 ,  H01L21/7602 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/76289

摘要： A silicon oxide layer is formed on a silicon substrate, and an opening whose wall is sloped inward is formed in the silicon oxide layer. A seed crystalline silicon layer is formed from the opening. The seed crystalline layer is selectively oxidized while leaving the seed crystalline layer required for crystal growth. An oxide formed at this time closes the opening. Consequently, the seed crystalline layer is insulated from the silicon substrate. The seed crystalline layer is epitaxially grown, to obtain a silicon growth layer on a field oxide layer. The growth layer is insulated from the silicon substrate, and is uniform in surface direction. Accordingly, there is no parasitic capacitance due to a p-n junction between the silicon substrate and the growth layer, thereby to make it possible to perform a high-speed operation. In addition, the growth layer is uniform in surface direction, thereby to make it easy to control the conditions set so as to obtain desired device characteristics in the manufacturing processes.

摘要翻译： 在硅衬底上形成氧化硅层，在氧化硅层上形成壁向内倾斜的开口部。 从开口形成晶种硅层。 籽晶层被选择性地氧化，同时留下晶体生长所需的晶种层。 此时形成的氧化物封闭开口。 因此，晶种层与硅衬底绝缘。 外延生长晶种层，以获得场氧化物层上的硅生长层。 生长层与硅衬底绝缘，表面方向均匀。 因此，由于硅衬底和生长层之间的p-n结，不存在寄生电容，从而能够执行高速操作。 此外，生长层在表面方向上是均匀的，从而使得容易控制设定的条件，以便在制造过程中获得期望的器件特性。

公开(公告)号：US20180315816A1

公开(公告)日：2018-11-01

申请号：US16027522

申请日：2018-07-05

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC分类号： H01L29/06

CPC分类号： H01L29/0653 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/7851

摘要： An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.