公开(公告)号：US20170271333A1

公开(公告)日：2017-09-21

申请号：US15611824

申请日：2017-06-02

申请人： SONY CORPORATION

发明人： MASAHIRO MITSUNAGA

IPC分类号： H01L27/095 ,  H01L21/28 ,  H01L41/25 ,  H01L41/08 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/205 ,  H01L29/10 ,  H01L29/778

CPC分类号： H01L27/095 ,  H01L21/28 ,  H01L21/8252 ,  H01L29/1066 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7785 ,  H01L29/7786 ,  H01L41/0815 ,  H01L41/25

摘要： A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

公开(公告)号：US09716187B2

公开(公告)日：2017-07-25

申请号：US14640240

申请日：2015-03-06

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Michael Thomason

IPC分类号： H01L27/06 ,  H01L27/095 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L29/8725 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66143

摘要： In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. The active trenches are configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

公开(公告)号：US09685345B2

公开(公告)日：2017-06-20

申请号：US14084335

申请日：2013-11-19

申请人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

IPC分类号： H01L29/15 ,  H01L21/311 ,  H01L29/872 ,  H01L29/66 ,  H01L23/544 ,  H01L29/47 ,  H01L29/778 ,  H01L27/06 ,  H01L27/095 ,  H01L21/027 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/0272 ,  H01L21/31111 ,  H01L23/544 ,  H01L27/0605 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/66431 ,  H01L29/812 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

公开(公告)号：US09673314B2

公开(公告)日：2017-06-06

申请号：US14794164

申请日：2015-07-08

申请人： Vishay-Siliconix

发明人： Chanho Park ,  Ayman Shibib ,  Kyle Terrill

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L27/095 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/872

摘要： A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

公开(公告)号：US09548353B2

公开(公告)日：2017-01-17

申请号：US14792991

申请日：2015-07-07

申请人： ROHM CO., LTD.

发明人： Masatoshi Aketa ,  Yuta Yokotsuji

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/872 ,  H01L21/04 ,  H01L21/265 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36

CPC分类号： H01L29/063 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/26546 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/872

摘要： A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C.

摘要翻译： 本发明的半导体器件包括由宽带隙半导体构成的半导体层和与半导体层的表面接触的肖特基电极。 半导体层包括形成半导体层的表面的漂移层和形成在漂移层的表面层部分上并且具有比漂移层更高的电阻的高电阻层。 通过从半导体层的表面注入杂质离子然后在小于1500℃进行退火处理来形成高电阻层。

公开(公告)号：US09536803B2

公开(公告)日：2017-01-03

申请号：US14847558

申请日：2015-09-08

申请人： RF Micro Devices, Inc.

发明人： David Charles Sheridan ,  Robert Charles Dry ,  Don Willis

IPC分类号： H01L23/34 ,  H01L25/07 ,  H05K7/20 ,  H01L27/095 ,  H01L27/088 ,  H01L29/10 ,  H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L29/423

CPC分类号： H01L23/345 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/49844 ,  H01L25/072 ,  H01L27/088 ,  H01L27/095 ,  H01L29/1079 ,  H01L29/4232 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K7/205 ,  H05K7/20963 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

摘要翻译： 具有耗尽型器件和增强型器件的集成电源模块被配置为在栅极信号丢失期间防止耗尽型器件的意外导通状态。 特别地，所公开的集成功率模块被构造成提供改进的隔离和导热性。 该结构包括具有用于耗尽型器件的底部漏极焊盘的衬底，其设置在衬底上，以及增强模式器件占位面积尺寸的空腔，其延伸穿过衬底到底部漏极焊盘。 导热和电绝缘的芯块基本上填充空腔，以在增强模式器件和用于耗尽型器件的底部漏极焊盘之间提供更高效的热路径。

公开(公告)号：US09431529B2

公开(公告)日：2016-08-30

申请号：US14625376

申请日：2015-02-18

申请人： Samsung Electronics Co., Ltd.

发明人： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

IPC分类号： H01L29/745 ,  H01L29/74 ,  H01L29/768 ,  H01L27/095 ,  H01L21/335 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

摘要： Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

摘要翻译： 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。

公开(公告)号：US09318487B2

公开(公告)日：2016-04-19

申请号：US13937542

申请日：2013-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jun-De Jin ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC分类号： H01L27/088 ,  H03F1/22 ,  H01L21/8238 ,  H01L27/095 ,  H03F3/213 ,  H01L27/092

CPC分类号： H01L27/0883 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/812 ,  H03F1/223 ,  H03F3/213

摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell.

摘要翻译： 为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P-基板中的N阱中的耗尽或肖特基MOSFET，其中水平或垂直通道介于 耗尽或肖特基MOSFET的源极，漏极和栅电极。 增强MOSFET的源节点和耗尽型或肖特基MOSFET的源极节点连接在一起形成功率单元。

公开(公告)号：US09165922B2

公开(公告)日：2015-10-20

申请号：US14015986

申请日：2013-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Akira Yoshioka ,  Yasunobu Saito ,  Hidetoshi Fujimoto ,  Takeshi Uchihara ,  Naoko Yanase ,  Toshiyuki Naka ,  Tetsuya Ohno ,  Tasuku Ono

IPC分类号： H01L27/06 ,  H01L27/095

CPC分类号： H01L27/0629 ,  H01L27/095 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/00014

摘要： According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

摘要翻译： 根据实施例，半导体器件包括导电衬底，肖特基势垒二极管和场效应晶体管。 肖特基势垒二极管安装在导电基板上，并包括阳极电极和阴极电极。 阳极电极与导电性基板电连接。 场效应晶体管安装在导电基板上，包括源电极，漏电极和栅电极。 场效应晶体管的源电极电连接到肖特基势垒二极管的阴极。 场效晶体管的栅电极与肖特基势垒二极管的阳极电连接。

公开(公告)号：US09142631B2

公开(公告)日：2015-09-22

申请号：US12725812

申请日：2010-03-17

申请人： Van Mieczkowski ,  Helmut Hagleitner ,  Zoltan Ring

发明人： Van Mieczkowski ,  Helmut Hagleitner ,  Zoltan Ring

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C.

摘要翻译： 半导体肖特基势垒器件包括宽带隙半导体层，宽带隙半导体层上的肖特基势垒金属层和形成肖特基结，在远离宽带隙半导体层的肖特基势垒金属层上的电流扩散层和两个或更多个扩散 电流扩散层和肖特基势垒金属层之间的阻挡层。 第一扩散阻挡层在约300℃以上的肖特基结温度下降低了电流扩散层和第二扩散阻挡层的混合，第二扩散阻挡层减少了第一扩散阻挡层和肖特基势垒金属层的混合 在高于约300℃的肖特基结的温度下