公开(公告)号：US07430128B2

公开(公告)日：2008-09-30

申请号：US10967541

申请日：2004-10-18

Applicant: William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

Inventor： William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1461 ,  Y10T29/435

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode, a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. This invention also relates to a method of making the device.

Abstract translation: 本发明涉及可以嵌入在印刷线路板的层内的电容/电阻装置。 嵌入器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 更具体地，该装置包括第一金属箔; 第二金属箔; 由所述第一金属箔形成的第一电极; 设置在所述第一电极上的电介质; 形成在电介质上并与其相邻的电阻元件; 导电迹线 以及由所述第二金属箔形成并且设置在所述电介质上并与所述电阻元件电接触的第二电极，其中所述电介质设置在所述第一电极和所述第二电极之间，并且其中所述电介质包括介电常数小于 4.0。 本发明还涉及制造该装置的方法。

公开(公告)号：US20080134499A1

公开(公告)日：2008-06-12

申请号：US12068272

申请日：2008-02-05

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/46

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract translation: 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20080121417A1

公开(公告)日：2008-05-29

申请号：US11623553

申请日：2007-01-16

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. The embedded capacitor is embedded in the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. The dielectric layer is laminated between the first and the second core circuit boards.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括第一核心电路板，至少一个嵌入式电容器，第二核心电路板和电介质层。 至少一个金属层设置在第一芯电路板的表面上，并且第一芯电路板的至少一个第一导电通孔连接到金属层。 嵌入式电容器嵌入第一个核心电路板并连接到金属层。 布线层设置在第二芯电路板的表面上，并且第二芯电路板的至少一个第二导电通孔连接到布线层。 介电层层叠在第一和第二核心电路板之间。

公开(公告)号：US07351915B2

公开(公告)日：2008-04-01

申请号：US10999442

申请日：2004-11-29

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: A printed circuit board (PCB) having at least one embedded capacitor and a method of fabricating the same is provided. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 提供了具有至少一个嵌入式电容器的印刷电路板（PCB）及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US20080037198A1

公开(公告)日：2008-02-14

申请号：US11502019

申请日：2006-08-10

Applicant: William J. Borland ,  David Ross McGregor ,  Daniel Irwin Amey ,  Matthew T. Onken

Inventor： William J. Borland ,  David Ross McGregor ,  Daniel Irwin Amey ,  Matthew T. Onken

IPC: H01G9/00

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/04 ,  H05K3/064 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/025

Abstract: Disclosed is a method of forming individual thin-film capacitors for embedding inside printed wiring boards or organic semiconductor package substrates, which includes removal of selective portions of the capacitor by sandblasting or other means so that the ceramic dielectric does not come in contact with acid etching solutions.

Abstract translation: 公开了一种形成用于嵌入印刷线路板或有机半导体封装基板内的各种薄膜电容器的方法，其包括通过喷砂或其它方式去除电容器的选择部分，使得陶瓷电介质不与酸蚀刻接触 解决方案

公开(公告)号：US07326643B2

公开(公告)日：2008-02-05

申请号：US11808596

申请日：2007-06-12

Applicant: Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

Inventor： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC: H01L21/4751

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract translation: 一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。

公开(公告)号：US20080003764A1

公开(公告)日：2008-01-03

申请号：US11479400

申请日：2006-06-30

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L21/20

CPC classification number: H05K1/162 ,  H05K1/112 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2203/0113 ,  H05K2203/0353 ,  H05K2203/061

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

公开(公告)号：US20070291440A1

公开(公告)日：2007-12-20

申请号：US11453359

申请日：2006-06-15

Applicant: Thomas E. Dueber ,  John D. Summers

Inventor： Thomas E. Dueber ,  John D. Summers

IPC: H01G4/00

CPC classification number: H05K1/162 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: Disclosed is an organic encapsulant composition that, when applied to formed-on-foil ceramic capacitors and embedded inside printed wiring boards, allows the capacitor to resist printed wiring board chemicals and survive accelerated life testing conducted under high humidity, elevated temperature and applied DC bias.

Abstract translation: 公开了一种有机密封剂组合物，当应用于箔上形成的陶瓷电容器和嵌入式印刷线路板时，允许电容器抵抗印刷线路板化学品并且在高湿度，高温和施加的直流偏压下进行加速寿命测试 。

公开(公告)号：US07301751B2

公开(公告)日：2007-11-27

申请号：US11229756

申请日：2005-09-19

Applicant: Jea-Hyuck Lee ,  Young-Min Lee ,  Shi-Yun Cho ,  Shin-Hee Cho ,  Kyung-Wan Park

Inventor： Jea-Hyuck Lee ,  Young-Min Lee ,  Shi-Yun Cho ,  Shin-Hee Cho ,  Kyung-Wan Park

IPC: H01G4/06 ,  H01G4/005 ,  H01G4/228

CPC classification number: H01G4/228 ,  H01G4/30 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09336 ,  H05K2201/09763

Abstract: An embedded capacitor comprises a first substrate on which a plurality of electrically insulated electrode patterns and a ground pattern are formed, a second substrate separated from the first substrate, a plurality of dielectric layers stacked between the first and second substrates, a plurality of metal layers inserted between the dielectric layers and connected to the electrode patterns of the first substrate, and a plurality of ground layers inserted between the dielectric layers alternately with the metal layers.

Abstract translation: 嵌入式电容器包括：第一基板，其上形成有多个电绝缘电极图案和接地图案;与第一基板分离的第二基板，堆叠在第一和第二基板之间的多个电介质层，多个金属层 插入在电介质层之间并连接到第一衬底的电极图案，以及多个接地层与金属层交替地插入在电介质层之间。

公开(公告)号：US20070249089A1

公开(公告)日：2007-10-25

申请号：US11808596

申请日：2007-06-12

Applicant: Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

Inventor： Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

IPC: H01L51/40

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract translation: 一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。