公开(公告)号：US07186149B2

公开(公告)日：2007-03-06

申请号：US11230442

申请日：2005-09-20

Applicant: Amid Hashim

Inventor： Amid Hashim

IPC: H01R24/00 ,  H01R13/625

CPC classification number: H05K1/0228 ,  H01R4/242 ,  H01R13/6469 ,  H01R13/6658 ,  H01R24/64 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communications connector includes: a dielectric mounting substrate; at least four pairs of conductors mounted on the mounting substrate, each of the conductors including a free end segment, each of the free end segments being positioned in side-by-side and generally parallel relationship; and at least four pairs of terminals mounted on the mounting substrate, wherein each of the pairs of terminals is electrically connected to a respective pair of conductors. A first pair of conductor free end segments is immediately adjacent each other, a second pair of conductor free end segments is immediately adjacent each other and positioned one side of the first pair, a fourth pair of conductor free end segments is immediately adjacent each other and positioned on an opposite side of the first pair, and a third pair of conductor free end segments sandwiches the first pair, with one of the conductor free end segments of the third pair being disposed between the first and second pairs, and the other of the conductor free end segments being disposed between the first and fourth pairs. Each of the first, second and fourth pairs of conductors includes a crossover between the conductors of the pairs, and the third pair of conductors includes three crossovers between its conductors.

Abstract translation: 通信连接器包括：电介质安装基板; 安装在所述安装基板上的至少四对导体，每个所述导体包括自由端段，每个所述自由端段以并排方式并且大致平行的关系定位; 以及安装在安装基板上的至少四对端子，其中每对端子电连接到相应的一对导体。 第一对导体自由端段彼此紧邻，第二对导体自由端段彼此紧邻并且位于第一对的一侧，第四对导体自由端段彼此紧邻， 定位在第一对的相对侧上，第三对导体自由端段夹住第一对，第三对中的一个导体自由端段设置在第一对和第二对之间，另一个 导体自由端段设置在第一和第四对之间。 第一，第二和第四对导体中的每一个包括在对的导体之间的交叉，并且第三对导体在其导体之间包括三个交叉。

公开(公告)号：US07170361B1

公开(公告)日：2007-01-30

申请号：US09548942

申请日：2000-04-13

Applicant: Warren M. Farnworth

Inventor： Warren M. Farnworth

IPC: H01P3/08

CPC classification number: H01P3/088 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K3/3436 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09336 ,  H05K2201/09618 ,  H01L2224/05599

Abstract: A method and apparatus for substantially reducing or eliminating electromagnetic and electrostatic coupling between signal traces on a substrate is disclosed. A substrate, such as a printed circuit board, is formed with an electrically insulative layer and a conductive layer. A portion of the conductive layer is removed to form circuit traces including signal traces and voltage reference traces configured such that each signal trace is separated from each other signal trace by at least one voltage reference trace. The invention is also applied to multiple layer printed circuit boards including a single voltage reference plane, an electronic system, and a semiconductor substrate. According to another aspect of the invention, a majority of a conductive layer is left on an insulative layer of a substrate by removing only those portions of the conductive layer immediately adjacent signal traces such that the remaining conductive material, which is ordinarily removed, acts to couple electromagnetic and electrostatic fields from the signal traces.

Abstract translation: 公开了用于基本上减少或消除基板上的信号迹线之间的电磁和静电耦合的方法和装置。 诸如印刷电路板的基板形成有电绝缘层和导电层。 导电层的一部分被去除以形成包括信号迹线和电压参考迹线的电路迹线，该迹线配置成使得每个信号迹线通过至少一个电压参考迹线与彼此信号迹线分离。 本发明也适用于包括单电压参考平面，电子系统和半导体衬底的多层印刷电路板。 根据本发明的另一方面，绝大多数导电层留在衬底的绝缘层上，通过仅去除与信号迹线紧邻的导电层的那些部分，使得通常被去除的剩余导电材料作用于 从信号迹线耦合电磁场和静电场。

公开(公告)号：US07084354B2

公开(公告)日：2006-08-01

申请号：US10173329

申请日：2002-06-14

Applicant: David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary I. Paek

Inventor： David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary I. Paek

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/115 ,  H05K3/4644 ,  H05K2201/09245 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49126

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.

公开(公告)号：US20060121791A1

公开(公告)日：2006-06-08

申请号：US11230442

申请日：2005-09-20

Applicant: Amid Hashim

Inventor： Amid Hashim

IPC: H01R24/00

CPC classification number: H05K1/0228 ,  H01R4/242 ,  H01R13/6469 ,  H01R13/6658 ,  H01R24/64 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communications connector includes: a dielectric mounting substrate; at least four pairs of conductors mounted on the mounting substrate, each of the conductors including a free end segment, each of the free end segments being positioned in side-by-side and generally parallel relationship; and at least four pairs of terminals mounted on the mounting substrate, wherein each of the pairs of terminals is electrically connected to a respective pair of conductors. A first pair of conductor free end segments is immediately adjacent each other, a second pair of conductor free end segments is immediately adjacent each other and positioned one side of the first pair, a fourth pair of conductor free end segments is immediately adjacent each other and positioned on an opposite side of the first pair, and a third pair of conductor free end segments sandwiches the first pair, with one of the conductor free end segments of the third pair being disposed between the first and second pairs, and the other of the conductor free end segments being disposed between the first and fourth pairs. Each of the first, second and fourth pairs of conductors includes a crossover between the conductors of the pairs, and the third pair of conductors includes three crossovers between its conductors.

Abstract translation: 通信连接器包括：电介质安装基板; 安装在所述安装基板上的至少四对导体，每个所述导体包括自由端段，每个所述自由端段以并排方式并且大致平行的关系定位; 以及安装在安装基板上的至少四对端子，其中每对端子电连接到相应的一对导体。 第一对导体自由端段彼此紧邻，第二对导体自由端段彼此紧邻并且位于第一对的一侧，第四对导体自由端段彼此紧邻， 定位在第一对的相对侧上，第三对导体自由端段夹住第一对，第三对中的一个导体自由端段设置在第一对和第二对之间，另一个 导体自由端段设置在第一和第四对之间。 第一，第二和第四对导体中的每一个包括在对的导体之间的交叉，并且第三对导体在其导体之间包括三个交叉。

公开(公告)号：US20050202697A1

公开(公告)日：2005-09-15

申请号：US11078816

申请日：2005-03-11

Applicant: Jack Caveney ,  Masud Bolouri-Saransar ,  Scott Lesniak

Inventor： Jack Caveney ,  Masud Bolouri-Saransar ,  Scott Lesniak

IPC: H01R12/00 ,  H01R13/66 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01R24/64 ,  H01R4/2429 ,  H01R4/2433 ,  H01R12/592 ,  H01R12/62 ,  H01R12/675 ,  H01R12/775 ,  H01R13/46 ,  H01R13/502 ,  H01R13/6461 ,  H01R13/6466 ,  H01R13/6467 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/62 ,  H01R2107/00 ,  H01R2201/04 ,  H05K1/0228 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49174 ,  Y10T29/49222

Abstract: An apparatus and method for crosstalk compensation in a jack of a modular communications connector includes a flexible printed circuit board connected to jack contacts and to connections to a network cable. The flexible printed circuit board includes conductive traces arranged as one or more couplings to provide crosstalk compensation.

Abstract translation: 用于模块化通信连接器的插座中的串扰补偿的装置和方法包括连接到插座触点和连接到网络电缆的柔性印刷电路板。 柔性印刷电路板包括布置成一个或多个耦合以提供串扰补偿的导电迹线。

公开(公告)号：US06916996B2

公开(公告)日：2005-07-12

申请号：US10605324

申请日：2003-09-23

Applicant: Chi-Kung Kuan ,  Chao-Cheng Lee ,  Kuan-Hua Lee

Inventor： Chi-Kung Kuan ,  Chao-Cheng Lee ,  Kuan-Hua Lee

IPC: H05K1/02 ,  H05K1/11 ,  H01R12/04

CPC classification number: H05K1/0245 ,  H05K1/115 ,  H05K2201/09245 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A symmetric electrical connection system for balancing impedance between a first node and a third node and impedance between a second node and a fourth node. The system includes a first conducting wire, a third conducting wire, a fifth conducting wire, and a seventh conducting wire all installed in a first layer. The system further includes a second conducting wire, a fourth conducting wire, a sixth conducting wire, and an eighth conducting wire all installed in a second layer. The first conducting wire and the eighth conducting wire are crossed but electrically insulated. The second conducting wire and the third conducting wire are crossed but electrically insulated. The fourth conducting wire and the fifth conducting wire are crossed but electrically insulated. The sixth conducting wire and the seventh conducting wire are crossed but electrically insulated. In a preferred embodiment, the appearances and the materials of the conducting wires are essentially equivalent.

Abstract translation: 一种用于平衡第一节点和第三节点之间的阻抗的对称电连接系统以及第二节点和第四节点之间的阻抗。 该系统包括全部安装在第一层中的第一导线，第三导线，第五导线和第七导线。 该系统还包括全部安装在第二层中的第二导线，第四导线，第六导线和第八导线。 第一导线和第八导线交叉但电绝缘。 第二导线和第三导线是交叉但电绝缘的。 第四导线和第五导线交叉但电绝缘。 第六导线和第七导线交叉但电绝缘。 在优选实施例中，导线的外观和材料基本相同。

公开(公告)号：US06855625B2

公开(公告)日：2005-02-15

申请号：US10458630

申请日：2003-06-11

Applicant: Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

Inventor： Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

IPC: H05K3/28 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01L21/47

CPC classification number: H05K3/4638 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/063 ,  H05K2203/065 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.

Abstract translation: 制备单面导体图案化膜，其每一个具有只形成树脂膜的一侧的导体图案和填充有导电浆料的通孔。 在单面导体图案化膜上层叠单面导体图案膜，其具有仅形成树脂膜的一侧的导体图案和形成在树脂膜中以露出电极的开口。 此外，在单面导体图案化膜的底面上层叠具有露出电极的开口的覆盖层，以形成层压体。 然后，通过在加热层叠体的同时按压，可以制造在其两侧具有电极的多层基板。

公开(公告)号：US06713848B2

公开(公告)日：2004-03-30

申请号：US10145972

申请日：2002-05-14

Applicant: Claus Neesgaard

Inventor： Claus Neesgaard

IPC: H01L2940

CPC classification number: H05K1/0216 ,  H03F3/2173 ,  H05K2201/09245 ,  H05K2201/1003

Abstract: An audio amplifier output stage layout technique achieves minimum cross coupling between audio amplifier channels. Regarding TDAA output stages, the typical TDAA includes two demodulation inductors per audio channel. The two pair of demodulation inductors associated with the TDAA are arranged to form an X-pattern to simultaneously minimize cross coupling between audio amplifier channels and reduce PCB layout size.

Abstract translation: 音频放大器输出级布局技术实现音频放大器通道之间的最小交叉耦合。 关于TDAA输出级，典型的TDAA每个音频通道包括两个解调电感。 与TDAA相关联的两对解调电感器被布置成形成X图案，以同时最小化音频放大器通道之间的交叉耦合并且减小PCB布局尺寸。

公开(公告)号：US20040057224A1

公开(公告)日：2004-03-25

申请号：US10627942

申请日：2003-07-25

Inventor： Frederick J. Kiko

IPC: H02B001/20

CPC classification number: H05K7/1435 ,  H01R31/005 ,  H01R2201/06 ,  H04Q1/10 ,  H04Q1/116 ,  H04Q1/155 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/117 ,  H05K1/14 ,  H05K1/181 ,  H05K7/1425 ,  H05K2201/044 ,  H05K2201/09245 ,  H05K2201/09709 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A high density electronics assembly which is highly modular in nature, thereby allowing a user to configure the assembly as desired for particular applications. The assembly also advantageously utilizes electronics inserts that are standardized across varying configurations, thereby obviating the need for different inserts for different applications. In one exemplary embodiment, the assembly comprises a low-profile Digital Subscriber Line (DSL) splitter apparatus, having a plurality of splitter circuits disposed within a housing structure in high density. Methods for manufacturing and configuring the assembly are also disclosed.

Abstract translation: 高密度电子组件本质上是高度模块化的，从而允许用户根据特定应用需要配置组件。 组件还有利地利用在不同配置上标准化的电子插件，从而避免了对不同应用的不同插入件的需要。 在一个示例性实施例中，组件包括低调数字用户线（DSL）分配器装置，其具有以高密度设置在壳体结构内的多个分离器电路。 还公开了用于制造和配置组件的方法。

公开(公告)号：US20030150643A1

公开(公告)日：2003-08-14

申请号：US10075356

申请日：2002-02-13

Inventor： Eric Juntwait ,  David F. Givens

IPC: H05K001/11

CPC classification number: H05K1/0228 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/114 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A printed circuit board (1) includes a plane substrate (10) having several insulated layers (11, 12, 13) used to dispose with conductive material. A row of footprints (2) used to connect to other electrical devices is disposed on an outer insulated layer (11) of the printed circuit board (1). These footprints (2) are paired and each is connected to a medial trace (5) formed on one of the intermediate layers (12) by a metalized hole (14). And the medial traces (C1, C1null) respectively connected to footprints (2) of the same pair (T1, R1) are formed on different intermediate layers (12) and aligned with each other for a predetermined distance. At least two traces (C3, C3null) connected to the chosen pair (T3, R3) are detoured to pass through a corresponding area aligned with the footprints (2) of their adjacent pair (T2, R2) mounted on the upper face (11) and are formed a corresponding footprint (R3null, T3null) over there respectively, so that the corresponding footprint (R3null, T3null) can be coupled with the footprints (T3, R3) to improve the noised signals received by the chosen pair (T3, R3) and its adjacent pair (T2, R2).

Abstract translation: 印刷电路板（1）包括具有用于与导电材料配置的几个绝缘层（11,12,13）的平面基板（10）。 在印刷电路板（1）的外绝缘层（11）上设置用于连接到其它电气设备的一排脚印（2）。 这些脚印（2）成对，并且每个通过金属化孔（14）连接到形成在中间层（12）之一上的中间迹线（5）。 并且分别连接到同一对（T1，R1）的脚印（2）的中间迹线（C1，C1'）形成在不同的中间层（12）上并且彼此对准预定距离。 连接到所选择的对（T3，R3）的至少两条迹线（C3，C3'）被绕开以通过与安装在上表面上的相邻对（T2，R2）的脚印（2）对准的对应区域 11），并在其上分别形成对应的占空比（R3'，T3'），使得相应的占空比（R3'，T3'）可与脚印（T3，R3）耦合，以改善由 选择对（T3，R3）及其相邻对（T2，R2）。