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    Neural network classifier using array of three-gate non-volatile memory cells
    345.
    发明授权
    Neural network classifier using array of three-gate non-volatile memory cells 有权

    公开(公告)号：US12283314B2

    公开(公告)日：2025-04-22

    申请号：US18644840

    申请日：2024-04-24

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H10B41/30 ,  H10D30/68

    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

    OUTPUT CIRCUIT FOR A VECTOR-BY-MATRIX MULTIPLICATION ARRAY
    347.
    发明申请
    OUTPUT CIRCUIT FOR A VECTOR-BY-MATRIX MULTIPLICATION ARRAY 有权

    公开(公告)号：US20250068900A1

    公开(公告)日：2025-02-27

    申请号：US18386901

    申请日：2023-11-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： HIEU VAN TRAN ,  ANDREW KUNIL CHOE ,  HOA VU

    IPC: G06N3/065

    Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W− weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.

    INPUT BLOCK FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY
    348.
    发明申请
    INPUT BLOCK FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY 有权

    公开(公告)号：US20250068861A1

    公开(公告)日：2025-02-27

    申请号：US18385344

    申请日：2023-10-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Stephen Trinh ,  Hoa Vu ,  Stanley Hong ,  Thuan Vu

    IPC: G06J1/00

    Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.

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