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    Semiconductor device and structure
    341.
    发明授权
    Semiconductor device and structure 有权
    半导体器件及结构

    公开(公告)号：US08686428B1

    公开(公告)日：2014-04-01

    申请号：US13678588

    申请日：2012-11-16

    Applicant: Monolithic 3D Inc.

    Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L21/70 ,  H01L21/822

    CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211

    Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.

    Abstract translation: 一种具有外表面的器件，该器件包括：包括第一单晶晶体管的衬底; 包括第二单晶晶体管的第二层，覆盖第一单晶晶体管的第二单晶晶体管; 以及从多个第二层位置到外表面的多个热传导路径，其中至少一个导热路径包括非导电接触。

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS
    344.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS 有权

    公开(公告)号：US20250070091A1

    公开(公告)日：2025-02-27

    申请号：US18942886

    申请日：2024-11-11

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

    Abstract: A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

    3D memory devices and structures with memory arrays and metal layers
    345.
    发明授权
    3D memory devices and structures with memory arrays and metal layers 有权

    公开(公告)号：US12225704B2

    公开(公告)日：2025-02-11

    申请号：US18731340

    申请日：2024-06-02

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H10B10/00 ,  G11C16/04 ,  H10B12/00 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS
    347.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS 有权

    公开(公告)号：US20240379553A1

    公开(公告)日：2024-11-14

    申请号：US18783965

    申请日：2024-07-25

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L23/528 ,  H01L21/66 ,  H01L23/522 ,  H10B80/00

    Abstract: A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.

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