公开(公告)号：US09768793B2

公开(公告)日：2017-09-19

申请号：US15365867

申请日：2016-11-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Qingdong Meng ,  Hajime Shibata ,  Richard E. Schreier ,  Martin Steven McCormick ,  Yunzhi Dong ,  Jose Barreiro Silva ,  Jialin Zhao ,  Donald W. Paterson ,  Wenhua W. Yang

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

公开(公告)号：US20170244388A1

公开(公告)日：2017-08-24

申请号：US15050875

申请日：2016-02-23

Applicant: ANALOG DEVICES GLOBAL

Inventor： Ahmed Mohammad Ashry Othman

IPC: H03H11/24

CPC classification number: H03H11/245

Abstract: Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.

公开(公告)号：US20170237268A1

公开(公告)日：2017-08-17

申请号：US15169981

申请日：2016-06-01

Applicant: Analog Devices Global

Inventor： Paraic Brannick ,  Colin G. Lyden ,  Damien J. McCartney ,  Gabriel Banarie

IPC: H02J7/00 ,  H03M1/20

CPC classification number: H02J7/007 ,  G04F10/005 ,  H02J7/345 ,  H03M1/201 ,  H03M1/50 ,  H03M1/52 ,  H03M1/60

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

公开(公告)号：US20170225942A1

公开(公告)日：2017-08-10

申请号：US15422508

申请日：2017-02-02

Applicant: Analog Devices Global

Inventor： Padraig Fitzgerald ,  Michael James Twohig

IPC: B81B3/00 ,  H01H59/00 ,  B81C1/00

CPC classification number: B81B3/0051 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0181 ,  B81C1/0015 ,  B81C2201/0109 ,  B81C2201/0197 ,  H01H59/0009 ,  H01H2059/0027 ,  H01H2059/0054

Abstract: Microelectromechanical systems (MEMS) switches are described. The MEMS switches can be actively opened and closed. The switch can include a beam coupled to an anchor on a substrate by one or more hinges. The beam, the hinges and the anchor may be made of the same material in some configurations. The switch can include electrodes, disposed on a surface of the substrate, for electrically controlling the orientation of the beam. The hinges may be thinner than the beam, resulting in the hinges being more flexible than the beam. In some configurations, the hinges are located within an opening in the beam. The hinges may extend in the same direction of the axis of rotation of the beam and/or in a direction perpendicular to the axis of rotation of the beam.

公开(公告)号：US20170207907A1

公开(公告)日：2017-07-20

申请号：US15336414

申请日：2016-10-27

Applicant: Analog Devices Global

Inventor： Mayur Gurunath Anvekar ,  Venkata Aruna Srikanth Nittala ,  Roberto Sergio Matteo Maurino ,  Naiqian Ren

IPC: H04L7/033 ,  H04L7/00 ,  H04L12/24

CPC classification number: H04L7/0331 ,  G01S7/521 ,  H04L7/0012 ,  H04L7/0029 ,  H04L41/0896

Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.

公开(公告)号：US09699542B2

公开(公告)日：2017-07-04

申请号：US14506062

申请日：2014-10-03

Applicant: Analog Devices Global

Inventor： Ulrik Sørensen Wismar ,  Sejun Kim

IPC: H04R1/10 ,  H04R29/00 ,  H03F3/187 ,  H03F3/45 ,  H04R5/033 ,  H04R5/04

CPC classification number: H04R1/1041 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/189 ,  H03F2203/45541 ,  H03F2203/45544 ,  H03F2203/45586 ,  H03F2203/45588 ,  H03F2203/45622 ,  H04R5/033 ,  H04R5/04 ,  H04R29/001

Abstract: A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g. a microphone preamplifier, configured to generate a microphone output voltage where the differential preamplifier comprises a first signal input coupled to the second terminal and a second signal input coupled to the third terminal of the connector interface. An error suppression circuit is configured to sense or sample a noise or error voltage at the second terminal when ground connected or the third terminal when ground connected. The error suppression circuit is further configured to add the sensed or sampled noise or error voltage to a predetermined DC bias voltage and generate an error compensated DC bias voltage for the ungrounded one of the second and third terminals of the connector interface.

公开(公告)号：US09698594B2

公开(公告)日：2017-07-04

申请号：US14937771

申请日：2015-11-10

Applicant: Analog Devices Global

Inventor： Edward John Coyne

IPC: H02H9/04 ,  H01L27/02 ,  H01L27/06 ,  H01L29/808 ,  H01L23/58

CPC classification number: H02H9/046 ,  H01L23/58 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/8083

Abstract: Components can be damaged if they are exposed to excess voltages. A device is disclosed herein which can be placed in series with a component and a node that may be exposed to high voltages. If the voltage becomes too high, the device can autonomously switch into a relatively high impedance state, thereby protecting the other components.

公开(公告)号：US20170179975A1

公开(公告)日：2017-06-22

申请号：US15360984

申请日：2016-11-23

Applicant: Analog Devices Global

Inventor： YUNZHI DONG ,  Hajime SHIBATA ,  Trevor Clifford CALDWELL ,  Zhao LI ,  Jialin ZHAO ,  Jose Barreiro SILVA

IPC: H03M3/00

CPC classification number: H03M3/422 ,  H03M1/361 ,  H03M3/322 ,  H03M3/344 ,  H03M3/378 ,  H03M3/388 ,  H03M3/414 ,  H03M3/436 ,  H03M3/464

Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

公开(公告)号：US20170179971A1

公开(公告)日：2017-06-22

申请号：US15282586

申请日：2016-09-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： ZHAO LI ,  HAJIME SHIBATA ,  TREVOR CLIFFORD CALDWELL ,  RICHARD E. SCHREIER ,  VICTOR KOZLOV ,  DAVID NELSON ALLDRED ,  PRAWAL MAN SHRESTHA

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/36

CPC classification number: H03M1/1023 ,  H03M1/1004 ,  H03M1/1038 ,  H03M1/1085 ,  H03M1/361 ,  H03M3/378 ,  H03M3/384

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

公开(公告)号：US20170179970A1

公开(公告)日：2017-06-22

申请号：US15369175

申请日：2016-12-05

Applicant: Analog Devices Global

Inventor： ZHAO LI ,  Hajime SHIBATA ,  Trevor Clifford CALDWELL ,  Yunzhi DONG ,  Jialin ZHAO ,  Richard E. SCHREIER ,  Victor KOZLOV ,  David Nelson ALLDRED ,  Prawal Man SHRESTHA

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/06 ,  H03M1/34 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/0626 ,  H03M1/066 ,  H03M1/1245 ,  H03M1/34 ,  H03M3/388 ,  H03M3/422

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.