公开(公告)号：US09391613B2

公开(公告)日：2016-07-12

申请号：US14884007

申请日：2015-10-15

Applicant: Rambus Inc.

Inventor： Huy M. Nguyen ,  Vijay Gadde ,  Benedict Lau

IPC: H03K19/003 ,  H03K19/00 ,  H04L25/02 ,  H03K19/01

CPC classification number: H03K19/0005 ,  H03K5/24 ,  H03K19/01 ,  H03K21/08 ,  H04L25/0278 ,  H04L25/0298

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

公开(公告)号：US09390798B2

公开(公告)日：2016-07-12

申请号：US14567988

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Wayne Frederick Ellis

IPC: G11C13/00 ,  G11C5/06 ,  G11C5/02

CPC classification number: G11C13/004 ,  G11C5/02 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。

公开(公告)号：US09390777B2

公开(公告)日：2016-07-12

申请号：US14821101

申请日：2015-08-07

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C7/00 ,  G11C7/22 ,  G06F13/16 ,  G06F13/40 ,  G11C8/18 ,  G11C11/4063

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US09389637B2

公开(公告)日：2016-07-12

申请号：US13867954

申请日：2013-04-22

Applicant: Rambus Inc.

Inventor： Huy Nguyen ,  Vijay Gadde ,  Kambiz Kaviani ,  Thomas Giovannini ,  Todd Bystrom

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。

公开(公告)号：US09385719B2

公开(公告)日：2016-07-05

申请号：US14619342

申请日：2015-02-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/0175 ,  G11C7/00 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US09373384B2

公开(公告)日：2016-06-21

申请号：US13845503

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Ravindranath Kollipara ,  Lei Luo ,  Ian Shaeffer

IPC: H03K19/003 ,  G11C11/401 ,  G11C5/04 ,  G11C7/10

CPC classification number: G11C11/401 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084

Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.

Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。

公开(公告)号：US09367248B2

公开(公告)日：2016-06-14

申请号：US14745746

申请日：2015-06-22

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L7/033 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US09362006B2

公开(公告)日：2016-06-07

申请号：US14570773

申请日：2014-12-15

Applicant: RAMBUS INC.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G06F1/04 ,  G01R23/00 ,  G01R23/10 ,  G01D21/00 ,  G01R35/00 ,  G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G01R23/15 ,  G11C7/04

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

Abstract translation: 所公开的实施例涉及支持定时漂移校准的存储器系统的组件。 在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。 存储装置还包括被配置为测量振荡器电路的频率的测量电路。 此外，存储器系统包含存储器控制器，该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。 存储器控制器还被配置为从存储器件接收测量的频率，并使用测量的频率来确定存储器件中的定时漂移。

公开(公告)号：US09356743B2

公开(公告)日：2016-05-31

申请号：US14318557

申请日：2014-06-27

Applicant: Rambus Inc.

Inventor： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

IPC: H04L1/24 ,  H04L1/00 ,  H04L5/14 ,  G01R31/3183 ,  G06F11/22 ,  G11C29/40 ,  H04B3/32 ,  H04B17/00 ,  H04L25/03 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/317 ,  G06F13/42 ,  G11C29/02 ,  G06F11/26

CPC classification number: H04L1/244 ,  G01R31/31703 ,  G01R31/31713 ,  G01R31/31716 ,  G01R31/31717 ,  G01R31/3183 ,  G01R31/31855 ,  G01R31/318577 ,  G01R31/3187 ,  G06F11/221 ,  G06F11/26 ,  G06F13/423 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/40 ,  H04B1/04 ,  H04B1/16 ,  H04B3/32 ,  H04B17/0085 ,  H04L1/0001 ,  H04L1/242 ,  H04L1/243 ,  H04L5/1438 ,  H04L25/03885

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

公开(公告)号：US09344635B2

公开(公告)日：2016-05-17

申请号：US14355799

申请日：2012-11-08

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  John Eric Linstadt ,  James E. Harris

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/235 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/353 ,  H04N1/00

CPC classification number: H04N5/235 ,  H04N1/00769 ,  H04N5/2355 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/35536 ,  H04N5/3745

Abstract: Pixel circuits in an image sensor are sampled repetitively during an image frame period. At each sampling, a signal indicative of the photocharge integrated by a pixel circuit since last reset is compared to a threshold. If the integrated photocharge signal has not reached the threshold, the pixel circuit is permitted to continue integrating photocharge. If the integrated photocharge signal has reached the threshold, the pixel circuit is reset to remove integrated photocharge and photocharge integration for that pixel circuit is restarted. A corresponding pixel circuit value is recorded for the reset pixel circuit.

Abstract translation: 图像传感器中的像素电路在图像帧周期期间重复采样。 在每次采样时，将与上一次复位后的像素电路集成的光电荷的信号与阈值进行比较。 如果集成光电荷信号尚未达到阈值，则允许像素电路继续积分光电荷。 如果积分的光电荷信号已经达到阈值，则像素电路被复位以去除集成的光电荷并且该像素电路的光电荷积分被重新启动。 记录复位像素电路的对应像素电路值。