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    SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR
    31.
    发明申请
    SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR 有权
    具有非标准形式因子的半导体存储器

    公开(公告)号：US20110185257A1

    公开(公告)日：2011-07-28

    申请号：US12693837

    申请日：2010-01-26

    申请人： Thomas Vogelsang

    发明人： Thomas Vogelsang

    IPC分类号： H03M13/05 ,  G06F11/10 ,  G06F12/02

    CPC分类号： G06F11/10 ,  G06F11/1048 ,  H03M13/19 ,  H03M13/2909

    摘要： A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

    摘要翻译： 一种半导体存储器芯片，包括错误校正电路，其被配置为从外部设备接收数据字，每个数据字包括二进制数量的数据位，并且被配置为对每个数据字进行错误编码以形成相应的编码字，所述对应的编码字包括非二进制数 数据位包括数据字的数据位和多个纠错码位。 至少一个存储单元阵列被配置为基于编码字的非二进制位数来接收和存储编码字并分区，以便具有非二进制数字的字线，并为存储器芯片提供宽高比 除了2：1的纵横比。

    Digitally controlled CML buffer
    35.
    发明授权
    Digitally controlled CML buffer 有权
    数字控制CML缓冲区

    公开(公告)号：US07965120B2

    公开(公告)日：2011-06-21

    申请号：US12275372

    申请日：2008-11-21

    申请人： Richard Lewison

    发明人： Richard Lewison

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133

    摘要： Techniques and corresponding circuits for achieving programmable delay of a current mode logic delay buffer are provided. The techniques provide for incremental delay with substantially equal increments. Delay may be achieved through the use of a circuit arrangement that allows biasing current to be controlled effect the response time of the circuit by digital control.

    摘要翻译： 提供了用于实现当前模式逻辑延迟缓冲器的可编程延迟的技术和相应的电路。 这些技术提供了基本上相等增量的增量延迟。 可以通过使用允许偏置电流被控制的电路布置来实现延迟，通过数字控制来影响电路的响应时间。

    Voltage regulation system
    36.
    发明授权
    Voltage regulation system 有权
    电压调节系统

    公开(公告)号：US07965066B2

    公开(公告)日：2011-06-21

    申请号：US10585151

    申请日：2004-11-23

    申请人： Martin Brox

    发明人： Martin Brox

    IPC分类号： G05F1/00 ,  G05F3/16 ,  G05F3/20

    CPC分类号： G05F1/465

    摘要： One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation system, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first device.

    摘要翻译： 本发明的一个方面涉及电压调节过程以及电压调节系统。 存在于电压调节系统的输入处的第一电压被改变成可以在电压调节系统的输出处被抽头的第二电压，第一电压用于从第一电压产生基本上恒定的电压，或 来自它的电压。 提供了另外的装置，用于从第一电压或从其导出的电压产生另外的电压，特别是可以高于由第一装置产生的电压的电压。

    Semiconductor memory and method for operating a semiconductor memory
    37.
    发明授权
    Semiconductor memory and method for operating a semiconductor memory 有权
    用于操作半导体存储器的半导体存储器和方法

    公开(公告)号：US07944725B2

    公开(公告)日：2011-05-17

    申请号：US12125684

    申请日：2008-05-22

    申请人： Roland Thewes ,  Michael Otto ,  Helmut Schneider

    发明人： Roland Thewes ,  Michael Otto ,  Helmut Schneider

    IPC分类号： G11C5/06

    CPC分类号： G11C11/4094 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

    摘要： A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier.

    摘要翻译： 半导体存储器具有多个读取放大器，其中两个互补位线中的每一个被连接到其上，其中半导体存储器包括用于每个位线的至少一个开关元件，通过该至少一个开关元件，位线的至少部分部分可以 与读取放大器电耦合，并且其中半导体存储器控制第一开关元件，使得第一开关元件在读出和/或刷新连接到位线的任何存储单元时暂时将至少部分部分断电 来自读取放大器的位线。

    Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor
    39.
    发明授权
    Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor 有权
    包括晶闸管的集成电路和控制包括晶闸管的存储单元的方法

    公开(公告)号：US07940558B2

    公开(公告)日：2011-05-10

    申请号：US12339722

    申请日：2008-12-19

    申请人： Stefan Slesazeck

    发明人： Stefan Slesazeck

    IPC分类号： G11C11/36

    CPC分类号： G11C11/39

    摘要： An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.

    摘要翻译： 提供了一种集成电路，其包括分别由字线和位线连接的存储单元的阵列，其中每个存储单元包括晶闸管结构，将晶闸管结构与相应位线连接的阳极端子，连接晶闸管的栅极端子 具有相应字线的结构和阴极端子。 集成电路还包括被配置为在阳极端子和栅极端子处施加电压信号的第一序列的驱动/感测电路，其中相对于阴极端子限定电压信号。 第一序列包括在阳极端子处的第一电压信号，在栅极端子处的第二电压信号，然后在阳极端子处组合第三电压信号和栅极端子处的第四电压信号，其中第三电压信号 低于第一电压信号且低于第四电压信号。

    Mask with registration marks and method of fabricating integrated circuits
    40.
    发明授权
    Mask with registration marks and method of fabricating integrated circuits 有权
    具有配准标记的掩模和制造集成电路的方法

    公开(公告)号：US07939224B2

    公开(公告)日：2011-05-10

    申请号：US11855234

    申请日：2007-09-14

    申请人： Andreas Jahnke ,  Ralf Ziebold ,  Torsten Maehr

    发明人： Andreas Jahnke ,  Ralf Ziebold ,  Torsten Maehr

    IPC分类号： G03F1/00 ,  G03C5/00

    CPC分类号： G03F9/7076 ,  G03F1/44

    摘要： A photomask for a lithography apparatus includes a chip pattern configured to be transferred into a resist layer on a workpiece and at least one registration mark that is configured not to be transferred into the resist layer. Mask qualification may be improved without impacting wafer level processes.

    摘要翻译： 用于光刻设备的光掩模包括被配置为转移到工件上的抗蚀剂层中的芯片图案和被配置为不被转移到抗蚀剂层中的至少一个配准标记。 可以改善掩模鉴定，而不影响晶片级处理。