公开(公告)号：US20110249279A1

公开(公告)日：2011-10-13

申请号：US13067652

申请日：2011-06-17

Applicant: Hee-Jin Lee

Inventor： Hee-Jin Lee

IPC: G06K15/02

CPC classification number: G06F3/1208 ,  G06F3/1205 ,  G06F3/1256 ,  G06F3/1284

Abstract: An apparatus and method are provided for setting a printing option using a preview image. Setting the printing option includes an image preview unit displaying a preview image corresponding to printing data and enabling the preview image to be manipulated for setting a printing setting, a control unit controlling printing of the preview image according to the printing setting of the manipulated preview image, and a printing option setting unit setting a printing option, wherein the control unit applies the printing setting of the preview image to the printing option of the printing option setting unit.

公开(公告)号：US07626261B2

公开(公告)日：2009-12-01

申请号：US11927457

申请日：2007-10-29

Applicant: Joong-Hyun Baek ,  Hee-Jin Lee

Inventor： Joong-Hyun Baek ,  Hee-Jin Lee

IPC: H01L23/34

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 以及填充冷却通孔内部的冷却剂。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20090129026A1

公开(公告)日：2009-05-21

申请号：US12292244

申请日：2008-11-14

Applicant: Joong-hyun Baek ,  Hee-jin Lee ,  Sun-won Kang

Inventor： Joong-hyun Baek ,  Hee-jin Lee ,  Sun-won Kang

IPC: H05K7/20

CPC classification number: H01L23/4093 ,  H01L23/3672 ,  H01L23/4275 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: Provided are a heat sink and a heat sink semiconductor module assembly which may include an improved, cooling function. Each of the heat sinks may include a flat heat sink base having a first surface attached to semiconductor devices and a second surface externally exposed; first fins provided on a portion of the second surface of the heat sink base to which no clip is coupled; and second fins provided on portions of the second surface of the heat sink base to which a clip may be coupled. The semiconductor module assembly may secure the heat sinks to both surfaces of a semiconductor module using the clip. Accordingly, air may flow smoothly through the second fins on the portions to which the clip may be coupled, thereby improving the cooling function of the heat sinks.

Abstract translation: 提供了散热器和散热半导体模块组件，其可以包括改进的冷却功能。 每个散热器可以包括平坦的散热器基座，其具有附接到半导体器件的第一表面和外部暴露的第二表面; 第一散热片设置在散热器基座的第二表面的没有夹子连接的部分上; 以及设置在所述散热器基座的所述第二表面的可以联接夹子的部分上的第二散热片。 半导体模块组件可以使用夹子将散热片固定到半导体模块的两个表面。 因此，空气可以平滑地流过夹子可以联接的部分上的第二鳍片，从而改善散热器的冷却功能。

公开(公告)号：US20080099909A1

公开(公告)日：2008-05-01

申请号：US11927457

申请日：2007-10-29

Applicant: Joong-Hyun BAEK ,  Hee-Jin LEE

Inventor： Joong-Hyun BAEK ,  Hee-Jin LEE

IPC: H01L23/34 ,  H01L21/58

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并密封; 形成在冷却通孔圆周上的微孔; 以及填充冷却通孔内部的冷却剂。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US07006503B1

公开(公告)日：2006-02-28

申请号：US09603615

申请日：2000-06-26

Applicant: Hee-jin Lee

Inventor： Hee-jin Lee

IPC: H04L12/28 ,  H04L12/66 ,  H04L12/403 ,  H04J3/16

CPC classification number: H04L12/64 ,  H04L69/16 ,  H04L69/166

Abstract: A method for matching an upper protocol layer to a high speed serial bus is provided. The method includes the steps of (a) determining whether the length of the data packet transferred from an upper layer to a node of the high speed serial bus is no less than a predetermined length, (b) allocating a channel of the bus and transferring data by an isochronous transfer service when it is determined that the length of the data packet is no less than the predetermined length, and (c) transferring data by an asynchronous transfer service when it is determined that the length of the data packet is less than the predetermined length. According to the above method, it is possible to match an existing communications application where it is not specified which service of the high speed serial bus is to be used to the high speed serial bus, while maintaining transparency of communication protocol and to effectively use the channel resources of the bus.

Abstract translation: 提供了将上层协议层与高速串行总线进行匹配的方法。 该方法包括以下步骤：（a）确定从高层串行总线的上层传送到节点的数据包的长度是否不小于预定长度，（b）分配总线的信道和传送 当确定数据分组的长度不小于预定长度时，通过同步传输服务的数据，以及（c）当确定数据分组的长度小于预定长度时，通过异步传输服务传送数据 预定长度。 根据上述方法，可以将不使用高速串行总线的哪个服务的现有通信应用与高速串行总线进行匹配，同时保持通信协议的透明性，并有效地使用 信道资源的总线。

公开(公告)号：US20160190109A1

公开(公告)日：2016-06-30

申请号：US14983510

申请日：2015-12-29

Applicant: Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

Inventor： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC: H01L25/16 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

Abstract translation: 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。

公开(公告)号：US20130163345A1

公开(公告)日：2013-06-27

申请号：US13605552

申请日：2012-09-06

Applicant: Sang Tae AHN ,  Gyu Seog Cho ,  Chae Moon Lim ,  Yoo Nam Jeon ,  Seung Hwan Baik ,  Hee Jin Lee ,  Jae Seok Kim ,  Kyung Sik Mun ,  U Seon Im

Inventor： Sang Tae AHN ,  Gyu Seog Cho ,  Chae Moon Lim ,  Yoo Nam Jeon ,  Seung Hwan Baik ,  Hee Jin Lee ,  Jae Seok Kim ,  Kyung Sik Mun ,  U Seon Im

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/3427

Abstract: A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.

Abstract translation: 一种操作半导体存储器件的方法包括：将第一电压施加到所选择的位线，将第二电压施加到未选定位线和公共源极线，以及接通漏极和源极选择晶体管的操作，施加编程电压 将选择的字线和开关电压切换到开关字线，并且将第一通过电压施加到设置在开关字线和公共源极线之间以及所选择的字线和位线之间的第一未选择字线，并且升高 所述开关电压产生热电子并将热电子注入到所选择的字线的选定的存储单元中以对所选择的单元进行编程。

公开(公告)号：US08310046B2

公开(公告)日：2012-11-13

申请号：US13235850

申请日：2011-09-19

Applicant: Joong-Hyun Baek ,  Hee-Jin Lee

Inventor： Joong-Hyun Baek ,  Hee-Jin Lee

IPC: H01L23/34

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L24/24 ,  H01L24/82 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15311

Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.

Abstract translation: 提供具有垂直发热路径的晶片叠层半导体封装（WSP）及其制造方法。 WSP包括其上安装有半导体芯片的基板; 在衬底上垂直堆叠的多个半导体芯片; 在多个半导体芯片中垂直形成的冷却通孔，并被密封; 形成在冷却通孔圆周上的微孔; 并且冷却剂填充在冷却通孔的内部。 因此，WSP降低了半导体芯片之间的温度差，并且迅速消散了堆叠的半导体芯片产生的热量。

公开(公告)号：US20120182569A1

公开(公告)日：2012-07-19

申请号：US13427566

申请日：2012-03-22

Applicant: Hee-Jin Lee

Inventor： Hee-Jin Lee

IPC: G06F3/12

CPC classification number: G06F3/1208 ,  G06F3/1205 ,  G06F3/1256 ,  G06F3/1284

Abstract: An apparatus and method are provided for setting a printing option using a preview image. Setting the printing option includes an image preview unit displaying a preview image corresponding to printing data and enabling the preview image to be manipulated for setting a printing setting, a control unit controlling printing of the preview image according to the printing setting of the manipulated preview image, and a printing option setting unit setting a printing option, wherein the control unit applies the printing setting of the preview image to the printing option of the printing option setting unit.

Abstract translation: 提供了一种用于使用预览图像设置打印选项的装置和方法。 设置打印选项包括图像预览单元，其显示对应于打印数据的预览图像，并且使得能够操纵预览图像以设置打印设置;控制单元，根据操作的预览图像的打印设置来控制预览图像的打印 以及设置打印选项的打印选项设置单元，其中控制单元将预览图像的打印设置应用于打印选项设置单元的打印选项。

公开(公告)号：US20120045871A1

公开(公告)日：2012-02-23

申请号：US13210607

申请日：2011-08-16

Applicant: Hee-Jin LEE ,  Joong-Hyun Baek

Inventor： Hee-Jin LEE ,  Joong-Hyun Baek

IPC: H01L21/56

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/0615 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Abstract translation: 提供半导体芯片，半导体模块，电子系统的半导体封装及其制造方法。 该方法包括将半导体芯片安装在封装基板上，在半导体芯片上形成模制构件，形成穿过模制构件的通孔以暴露半导体芯片的顶表面的一部分，通孔布置成格子状 并且在通孔中通过塞子形成热传导。