公开(公告)号：US20070120580A1

公开(公告)日：2007-05-31

申请号：US11403902

申请日：2006-04-14

Applicant: Dong Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Sun-ae Seo ,  In-gyu Baek ,  Seung-eon Ahn ,  Byoung-ho Park ,  Young-kwan Cha ,  Sang-jin Park

Inventor： Dong Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Sun-ae Seo ,  In-gyu Baek ,  Seung-eon Ahn ,  Byoung-ho Park ,  Young-kwan Cha ,  Sang-jin Park

IPC: H03K19/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract translation: 存储器件可以包括与开关器件耦合的开关器件和存储节点。 存储节点可以包括第一电极，第二电极，数据存储层和至少一个接触层。 数据存储层可以设置在第一电极和第二电极之间，并且可以包括过渡金属氧化物或氧化铝。 至少一个接触层可以设置在数据存储层的上方或下方的至少一个上，并且可以包括导电金属氧化物。

公开(公告)号：US20070045692A1

公开(公告)日：2007-03-01

申请号：US11511469

申请日：2006-08-29

Applicant: Dong-Chul Kim ,  In-Gyu Baek ,  Young-Kwan Cha ,  Moon-Sook Lee ,  Sang-Jin Park

Inventor： Dong-Chul Kim ,  In-Gyu Baek ,  Young-Kwan Cha ,  Moon-Sook Lee ,  Sang-Jin Park

IPC: H01L29/94

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract translation: 提供了非易失性存储器件及其制造方法。 非易失性存储器件可以包括由电阻转换材料，下电极，由下电极上的过渡金属形成的纳米线层和形成在氧化物层上的上电极形成的氧化物层。 根据示例性实施例，可以通过统一氧化物层上的电流路径来稳定复位电流。

公开(公告)号：US07141438B2

公开(公告)日：2006-11-28

申请号：US10915872

申请日：2004-08-10

Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

Abstract translation: 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

公开(公告)号：US20060097288A1

公开(公告)日：2006-05-11

申请号：US11241604

申请日：2005-09-30

Applicant: In-Gyu Baek ,  Moon-Sook Lee

Inventor： In-Gyu Baek ,  Moon-Sook Lee

IPC: H01L21/82 ,  H01L27/10

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower electrodes are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer is provided between the upper electrodes and the lower electrodes and provided as a data storage material layer. Doped regions are provided between the lower electrodes and the doped lines and form diodes together with the doped lines. The doped regions have an opposite polarity to the doped lines

Abstract translation: 使用二元金属氧化物层作为数据存储材料层的交叉点非易失性存储器件包括设置在衬底中的间隔开的掺杂线。 间隔开的上电极在掺杂线上交叉，使得形成交叉点，其中上电极与掺杂线重叠。 下电极设置在掺杂线和上电极之间的交叉点处。 在上部电极和下部电极之间设置二元金属氧化物层，作为数据存储材料层。 掺杂区域设置在下电极和掺杂线之间，并与掺杂线一起形成二极管。 掺杂区域具有与掺杂线相反的极性

公开(公告)号：US20050006682A1

公开(公告)日：2005-01-13

申请号：US10888964

申请日：2004-07-09

Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

IPC: G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/12 ,  H01L29/76 ,  G11B5/127

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11B5/3909 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/302 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括下电极和下电极上的磁隧道结。 磁性隧道结包括种子层和隧道势垒，其定向在与种子层的最紧密堆积的平面方向相同的方向上。 可以在下电极和磁隧道结之间提供氧化物层。 下电极可以是具有超过50原子％钛含量的富钛TiN层。 还描述了类似的制造方法。

公开(公告)号：US08737112B2

公开(公告)日：2014-05-27

申请号：US13238669

申请日：2011-09-21

Applicant: Chul Woo Park ,  In Gyu Baek ,  Dong Hyun Sohn ,  Hong Sun Hwang

Inventor： Chul Woo Park ,  In Gyu Baek ,  Dong Hyun Sohn ,  Hong Sun Hwang

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/79

Abstract: A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.

Abstract translation: 提供了电阻式存储器件和初始化方法。 电阻性存储器件包括连接在位线与第一板之间的第一组电阻存储器单元和连接在位线和第二板之间的第二组。 第一和第二初始化电压分别施加到与电阻存储器单元的正常操作相关联的正常路径之外的第一和第二板。

公开(公告)号：US08634227B2

公开(公告)日：2014-01-21

申请号：US13184795

申请日：2011-07-18

Applicant: Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A Kim ,  Mu Jin Seo

Inventor： Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A Kim ,  Mu Jin Seo

IPC: G11C11/00

CPC classification number: G11C8/14 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71

Abstract: Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.

Abstract translation: 提供了半导体电阻式存储器件。 电阻式存储器件包括多个单元电池。 单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。 均衡可能会降低电流消耗并保护写入错误，并保护漏电流。

公开(公告)号：US08525247B2

公开(公告)日：2013-09-03

申请号：US13462844

申请日：2012-05-03

Applicant: Chan-Jin Park ,  Hyun-Su Ju ,  In-Gyu Baek

Inventor： Chan-Jin Park ,  Hyun-Su Ju ,  In-Gyu Baek

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.

Abstract translation: 非易失性存储器件包括下成型层，下成型层上的水平互连线，水平互连线上的上成型层，垂直穿过上成型层，水平互连线和下成型件的柱 层和介于柱和成型层之间的缓冲层。 该装置还包括可变电阻材料和插在支柱和水平互连线之间的二极管层。

公开(公告)号：US08472237B2

公开(公告)日：2013-06-25

申请号：US12943465

申请日：2010-11-10

Applicant: Jeong-hoon Oh ,  Kyung-chang Ryoo ,  Byung-gook Park ,  Kyung-seok Oh ,  In-gyu Baek

Inventor： Jeong-hoon Oh ,  Kyung-chang Ryoo ,  Byung-gook Park ,  Kyung-seok Oh ,  In-gyu Baek

IPC: G11C11/21

CPC classification number: G11C13/0002 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/102 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch between low resistance states and high resistance states, respectively, according to an applied voltage.

Abstract translation: 示例性实施例公开了使用电阻性存储器材料层的半导体器件和驱动该半导体器件的方法。 半导体器件包括多个存储单元。 至少一个存储单元包括单极性可变电阻器和双极可变电阻器，其串联连接并且被配置为根据施加的电压分别在低电阻状态和高电阻状态之间切换。

公开(公告)号：US08456891B2

公开(公告)日：2013-06-04

申请号：US13150596

申请日：2011-06-01

Applicant: In-gyu Baek ,  Myung-jong Kim ,  Yong-ho Ha

Inventor： In-gyu Baek ,  Myung-jong Kim ,  Yong-ho Ha

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory cell includes first and second electrodes and a data storage layer extending between the first and second electrodes. An oxygen diffusion barrier layer is provided, which extends between the data storage layer and the first electrode. An oxygen gettering layer is also provided, which extends between the oxygen diffusion barrier layer and the data storage layer. The oxygen diffusion barrier layer includes aluminum oxide, the oxygen gettering layer includes titanium, the data storage layer includes a metal oxide, such as magnesium oxide, and at least one of the first and second electrodes includes a material selected from a group consisting of tungsten, polysilicon, aluminum, titanium nitride silicide and conductive nitrides.

Abstract translation: 非易失性存储单元包括第一和第二电极以及在第一和第二电极之间延伸的数据存储层。 提供氧扩散阻挡层，其在数据存储层和第一电极之间延伸。 还提供了氧吸气层，其在氧扩散阻挡层和数据存储层之间延伸。 氧扩散阻挡层包括氧化铝，氧吸气层包括钛，数据存储层包括诸如氧化镁的金属氧化物，并且第一和第二电极中的至少一个包括选自钨 ，多晶硅，铝，氮化钛硅化物和导电氮化物。