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    Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line
    31.
    发明授权
    Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line 有权
    通过对所选择的字线施加比毗邻所选字线的字线更高的电压电平来对非易失性闪存器件进行编程的方法

    公开(公告)号：US08248853B2

    公开(公告)日：2012-08-21

    申请号：US12590701

    申请日：2009-11-12

    申请人： Jae Duk Lee ,  Soon Moon Jung ,  Jung Dal Choi

    发明人： Jae Duk Lee ,  Soon Moon Jung ,  Jung Dal Choi

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

    摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.

    摘要翻译： 在编程非易失性存储器件的方法中，将第一电压施加到对应于要编程的所选择的晶体管串的选定存储单元晶体管的选定字线; 第二电压被施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中第一电压大于第二电压，将第一和第二电压施加到所选择的和 分别使相邻的晶体管与所选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选存储单元晶体管的电荷存储层中; 其中所述相邻晶体管位于所选择的存储单元晶体管和接地选择晶体管和串选择晶体管中的一个之间，并且所述第一电压被施加到对应于所选择的晶体管串的未选择存储单元晶体管的未选择字线， 存储单元晶体管和另一个接地选择晶体管和串选择晶体管。

    Semiconductor Memory Device Having Three Dimensional Structure
    32.
    发明申请
    Semiconductor Memory Device Having Three Dimensional Structure 审中-公开
    具有三维结构的半导体存储器件

    公开(公告)号：US20110266623A1

    公开(公告)日：2011-11-03

    申请号：US13185184

    申请日：2011-07-18

    申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    IPC分类号： H01L27/12

    CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

    摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

    Non-volatile memory device and method of operating the same
    33.
    发明授权
    Non-volatile memory device and method of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08040733B2

    公开(公告)日：2011-10-18

    申请号：US12486924

    申请日：2009-06-18

    申请人： Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

    发明人： Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.

    摘要翻译： 非易失性存储器件包括分别连接到第一串存储单元晶体管的栅极的第一和第二串存储单元晶体管，相关的第一和第二字线，其中相应的第一和第二字线被连接以共同接收偏置电压。 非易失性存储器件还包括连接到第一和第二串的虚拟单元晶体管，以及被配置为接收不同偏置电压的第一和第二虚拟字线。

    MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF
    34.
    发明申请
    MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF 有权
    多层非易失性存储器件，使用这种器件的存储器系统及其制造方法

    公开(公告)号：US20110171787A1

    公开(公告)日：2011-07-14

    申请号：US13069869

    申请日：2011-03-23

    申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    IPC分类号： H01L21/8246

    CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

    摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

    摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

    Semiconductor memory devices having vertically-stacked transistors therein
    35.
    发明授权
    Semiconductor memory devices having vertically-stacked transistors therein 有权
    其中具有垂直堆叠的晶体管的半导体存储器件

    公开(公告)号：US07978561B2

    公开(公告)日：2011-07-12

    申请号：US12408932

    申请日：2009-03-23

    申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    IPC分类号： G11C8/00

    CPC分类号： G11C11/412 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/08 ,  G11C8/12 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.

    摘要翻译： 提供了具有堆叠结构的晶体管的半导体器件。 具有晶体管的半导体存储器件包括存储单元阵列块，其包括多个字线和多个存储单元，每个存储单元包括连接在多个字线之间的至少一个第一晶体管，以及包括多个字线的字线解码器 分别驱动多个字线的驱动器，其中多个字线被布置在第一层上，并且多个驱动器设置在至少两个第二层上。

    3-dimensional flash memory device, method of fabrication and method of operation
    36.
    发明授权
    3-dimensional flash memory device, method of fabrication and method of operation 失效
    3维闪存器件，制造方法和操作方法

    公开(公告)号：US07960844B2

    公开(公告)日：2011-06-14

    申请号：US12499980

    申请日：2009-07-09

    申请人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

    发明人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

    摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

    摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

    Semiconductor device with three-dimensional array structure
    38.
    发明授权
    Semiconductor device with three-dimensional array structure 有权
    具有三维阵列结构的半导体器件

    公开(公告)号：US07646664B2

    公开(公告)日：2010-01-12

    申请号：US11869140

    申请日：2007-10-09

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

    摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

    NAND-type non-volatile memory devices having a stacked structure
    39.
    发明授权
    NAND-type non-volatile memory devices having a stacked structure 失效
    具有堆叠结构的NAND型非易失性存储器件

    公开(公告)号：US07626228B2

    公开(公告)日：2009-12-01

    申请号：US11637686

    申请日：2006-12-12

    申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

    摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

    摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。