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    Method and apparatus for managing power in a thermal couple aware system
    32.
    发明授权
    Method and apparatus for managing power in a thermal couple aware system 有权

    公开(公告)号：US10955884B2

    公开(公告)日：2021-03-23

    申请号：US15071643

    申请日：2016-03-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Huang ,  Manish Arora ,  Abhinandan Majumdar ,  Indrani Paul ,  Leonardo de Paula Rosa Piga

    IPC: G06F1/20 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296

    Abstract: A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.

    Determining thermal time constants of processing systems
    33.
    发明授权
    Determining thermal time constants of processing systems 有权

    公开(公告)号：US10281964B2

    公开(公告)日：2019-05-07

    申请号：US15010965

    申请日：2016-01-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrain Paul ,  Wei Huang ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F11/30

    Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

    HARDWARE AND RUNTIME COORDINATED LOAD BALANCING FOR PARALLEL APPLICATIONS
    36.
    发明申请
    HARDWARE AND RUNTIME COORDINATED LOAD BALANCING FOR PARALLEL APPLICATIONS 有权
    硬件和运行协调负载均衡并行应用

    公开(公告)号：US20160259667A1

    公开(公告)日：2016-09-08

    申请号：US14641220

    申请日：2015-03-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Peter Bailey ,  Indrani Paul ,  Manish Arora

    IPC: G06F9/50

    CPC classification number: G06F9/505 ,  G06F1/3243 ,  G06F1/329 ,  G06F8/443 ,  G06F9/30065 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/4893 ,  G06F9/5094 ,  G06F9/522 ,  G06F2209/5019 ,  Y02D10/152 ,  Y02D10/24

    Abstract: A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.

    Abstract translation: 一种平衡处理器并行执行的多个并行程序循环的执行率的方法可以包括：估计多个程序循环中每个程序循环的完成时间，确定第一程序循环的估计完成时间之间的差异 所述多个程序循环的多个程序循环和所述多个程序循环的第二程序循环的估计完成时间，以及通过调整所述第一程序循环的执行速率来减小所述差异。

    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING
    39.
    发明申请
    DECOUPLED ENTRY AND EXIT PREDICTION FOR POWER GATING 有权
    放弃进入和退出预测功率增益

    公开(公告)号：US20150370311A1

    公开(公告)日：2015-12-24

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32 ,  G06N5/04

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS
    40.
    发明申请
    POWER MANAGEMENT ACROSS HETEROGENEOUS PROCESSING UNITS 有权
    电源管理异步加工单元

    公开(公告)号：US20150355692A1

    公开(公告)日：2015-12-10

    申请号：US14297208

    申请日：2014-06-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F9/50 ,  G06F11/30 ,  G06F1/32

    CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3447 ,  Y02D10/126 ,  Y02D10/22

    Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

    Abstract translation: 一种方法包括基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的活动频率状态。 处理器包括多个异构处理单元和性能控制器，用于基于指示多个异构处理单元中的不同类型的处理单元之间的性能耦合的频率灵敏度度量来控制多个异构处理单元的有效频率状态。 基于与第一类型处理单元相关联的第一活动度量和与第二类型处理单元相关联的第二活动度量来控制多个异构处理单元中的第一类型处理单元的活动频率状态。

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