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公开(公告)号：US09865648B2
公开(公告)日：2018-01-09
申请号：US14109604
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： Paul I. Bunyk
CPC classification number: H01L27/18 , G01R31/2884 , G01R31/2891 , H01L24/05 , H01L24/13 , H01L24/81 , H01L39/045 , H01L39/24 , H01L2224/0401 , H01L2224/05008 , H01L2224/05023 , H01L2224/05179 , H01L2224/05548 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611 , H01L2224/13007 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13163 , H01L2224/13176 , H01L2224/13183 , H01L2224/13562 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13611 , H01L2224/16238 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/15787 , H01L2924/35121 , H01L2924/00014 , H01L2924/014 , H01L2924/01076 , H01L2224/81 , H01L2924/00
Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.
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32.发明授权公开(公告)号：US09699266B2
公开(公告)日：2017-07-04
申请号：US14162557
申请日：2014-01-23
Applicant: D-Wave Systems Inc.
Inventor： Geordie Rose , Paul I. Bunyk
CPC classification number: H04L67/34 , G06F15/7825 , G06N99/002 , H04B10/70 , H04L45/306 , H04L67/327 , H04Q11/0066 , H04Q2011/0073
Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.
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33.发明申请SYSTEMS, METHODS AND APPARATUS FOR ACTIVE COMPENSATION OF QUANTUM PROCESSOR ELEMENTS 有权用于量子处理器元件的主动补偿的系统，方法和装置公开(公告)号：US20150379418A1
公开(公告)日：2015-12-31
申请号：US14846334
申请日：2015-09-04
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
CPC classification number: H01L39/223 , B82Y10/00 , G06N99/002 , H01L27/18
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Abstract translation: 装置和方法使得能够对量子处理器的超导元件中的不期望的差异进行主动补偿。 量子位可以包括主复合约瑟夫逊结（CJJ）结构，其可以包括至少第一次级CJJ结构，以能够补偿主CJJ结构中的约瑟夫逊结不对称性。 量子位可以包括与第一CJJ结构并联耦合以提供可调电容的串联LC电路。 量子位控制系统可以包括用于调整量子位环路的电感的装置，例如感应耦合到量子位循环并由编程接口控制的可调谐耦合器件，或与量子位循环串联耦合并由编程接口控制的CJJ结构 。
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公开(公告)号：US20150346291A1
公开(公告)日：2015-12-03
申请号：US14462200
申请日：2014-08-18
Applicant: D-Wave Systems Inc.
Inventor： Trevor Michael Lanting , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Sergey V. Uchaykin , Andrew Brock Wilson , Mark Johnson
IPC: G01R33/035 , G01R33/00
CPC classification number: G01R33/0354 , G01R33/0017 , G01R33/0094
Abstract: SQUIDs may detect local magnetic fields. SQUIDS of varying sizes, and hence sensitivities may detect different magnitudes of magnetic fields. SQUIDs may be oriented to detect magnetic fields in a variety of orientations, for example along an orthogonal reference frame of a chip or wafer. The SQUIDS may be formed or carried on the same chip or wafer as a superconducting processor (e.g., a superconducting quantum processor). Measurement of magnetic fields may permit compensation, for example allowing tuning of a compensation field via a compensation coil and/or a heater to warm select portions of a system. A SQIF may be implemented as a SQUID employing an unconventional grating structure. Successful fabrication of an operable SQIF may be facilitated by incorporating multiple Josephson junctions in series in each arm of the unconventional grating structure.
Abstract translation: SQUID可以检测局部磁场。 具有不同尺寸的SQUIDS，因此灵敏度可以检测不同的磁场强度。 SQUID可以被定向以检测各种取向中的磁场，例如沿着芯片或晶片的正交参考系。 SQUIDS可以与超导处理器（例如超导量子处理器）形成或携带在相同的芯片或晶片上。 磁场的测量可以允许补偿，例如允许通过补偿线圈和/或加热器对补偿场进行调谐以温暖系统的选择部分。 SQIF可以被实现为采用非常规光栅结构的SQUID。 可以通过将多个约瑟夫逊结串联在非常规光栅结构的每个臂中来促进可操作的SQIF的成功制造。
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35.发明申请公开(公告)号：US20150119252A1
公开(公告)日：2015-04-30
申请号：US14383837
申请日：2013-03-07
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
CPC classification number: H01L39/2493 , B82Y10/00 , G06N99/002 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
Abstract translation: 各种技术和装置允许制造超导电路。 可以形成铌/氧化铝/铌三层，并形成单个的约瑟夫逊结（JJ）。 保护盖可以在制造过程中保护JJ。 可以形成混合电介质。 可以使用减法图案化和/或添加剂图案化来形成超导集成电路。 可以通过电镀和/或通过化学机械平面化抛光来沉积超导金属层。 内层电介质的厚度可以通过沉积工艺来控制。 衬底可以包括硅的基底和包括氧化铝的顶层。 可以停止或暂停超导金属层的沉积，以在完成之前进行冷却。 可以通过在超导金属层中图案化对准标记物来对准多个层。
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Patent Agency Ranking
公开(公告)号：US12034404B2
公开(公告)日：2024-07-09
申请号：US17158484
申请日：2021-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
CPC classification number: H03B15/003 , G06N10/20 , G06N10/40 , H01P7/08 , H01P7/105 , H03H7/01 , H10N60/12 , G06N10/00 , H03B2201/02
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US11930721B2
公开(公告)日：2024-03-12
申请号：US16870537
申请日：2020-05-08
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H10N60/01 , B82Y10/00 , H01L21/285 , H01L21/768 , H10N60/10 , H10N60/12 , H10N60/80 , H10N60/85 , H10N69/00 , G06N10/00
CPC classification number: H10N60/0912 , B82Y10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H10N60/01 , H10N60/0156 , H10N60/10 , H10N60/12 , H10N60/805 , H10N60/855 , H10N69/00 , G06N10/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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38.发明公开公开(公告)号：US20230143506A1
公开(公告)日：2023-05-11
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US11514223B2
公开(公告)日：2022-11-29
申请号：US17068388
申请日：2020-10-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Paul I. Bunyk
IPC: G06F30/398 , G06N10/00 , G06F30/392 , G06F115/12
Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.
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公开(公告)号：US20210218367A1
公开(公告)日：2021-07-15
申请号：US17158484
申请日：2021-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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