公开(公告)号：US09356119B2

公开(公告)日：2016-05-31

申请号：US13770545

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485 ,  H01L29/165

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.

公开(公告)号：US09324796B2

公开(公告)日：2016-04-26

申请号：US14751646

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09324790B2

公开(公告)日：2016-04-26

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09318578B2

公开(公告)日：2016-04-19

申请号：US13628561

申请日：2012-09-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Abstract translation: 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

公开(公告)号：US09305846B2

公开(公告)日：2016-04-05

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US09293532B2

公开(公告)日：2016-03-22

申请号：US14751542

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US20150372080A1

公开(公告)日：2015-12-24

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09214567B2

公开(公告)日：2015-12-15

申请号：US14020096

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/44 ,  H01L29/786 ,  H01L23/62 ,  H01L27/02

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract translation: 在半导体衬底的一个区域中设置电熔丝。 电子熔断器包括从底部到顶部的基底金属半导体合金部分，第一金属半导体合金部分，第二金属半导体部分，第三金属半导体合金部分和第四金属半导体合金部分的垂直堆叠，其中 第一金属半导体合金部分和第三金属半导体部分具有垂直偏移并且不延伸超过第二金属半导体合金部分和第四金属半导体合金部分的垂直边缘的外边缘。

公开(公告)号：US08963259B2

公开(公告)日：2015-02-24

申请号：US13906852

申请日：2013-05-31

Applicant: GlobalFoundries Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Steven J. Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/761 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.