公开(公告)号：US20190081597A1

公开(公告)日：2019-03-14

申请号：US15701672

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Alvin J. Joseph ,  John J. Pekarik

IPC: H03F1/22 ,  H01L27/07 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

公开(公告)号：US10164101B1

公开(公告)日：2018-12-25

申请号：US15790707

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Anthony K. Stamper ,  Vibhor Jain ,  Mark D. Jaffe

IPC: H01L21/82 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.

公开(公告)号：US20180226292A1

公开(公告)日：2018-08-09

申请号：US15425384

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76289 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/7317 ,  H01L29/7371 ,  H01L29/78 ,  H01L2221/68345

Abstract: Structures with trench isolation and methods for making a structure with trench isolation. A transistor is formed by front-end-of-line processing on a first surface of a semiconductor substrate. A barrier layer is formed by middle-of-line processing on the transistor and the first surface of the semiconductor substrate. After the transistor and the barrier layer are formed, a trench is etched into the semiconductor substrate from a second surface of the semiconductor substrate that is opposite from the first surface of the semiconductor substrate. The trench, which is used to form an isolation region, may terminate on a dielectric layer associated with the transistor or may terminate on the barrier layer.

公开(公告)号：US09966310B1

公开(公告)日：2018-05-08

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US20170330832A1

公开(公告)日：2017-11-16

申请号：US15152794

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/4821 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1203

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09761526B2

公开(公告)日：2017-09-12

申请号：US15014759

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US09761525B1

公开(公告)日：2017-09-12

申请号：US15142525

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Terence B. Hook ,  Richard A. Phelps ,  Anthony K. Stamper ,  Renata A. Camillo-Castillo

IPC: H01L29/76 ,  H01L29/94 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/7831 ,  H01L29/7832 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

公开(公告)号：US20170186693A1

公开(公告)日：2017-06-29

申请号：US14982097

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US20170140865A1

公开(公告)日：2017-05-18

申请号：US14942311

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F21/12 ,  H01F41/041 ,  H01F2027/2809

Abstract: This disclosure relates generally to semiconductors, and more particularly, to structures and methods for implementing high performance multi-frequency inductors with airgaps or other low-k dielectric material. The structure includes: a plurality of concentric conductive bands; a low-k dielectric area selectively placed between inner windings of the plurality of concentric conductive bands; and insulator material with a higher-k dielectric material than the low-k dielectric area selectively placed between remaining windings of the plurality of concentric conductive bands.

公开(公告)号：US09653566B2

公开(公告)日：2017-05-16

申请号：US14958345

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.