公开(公告)号：US20160358826A1

公开(公告)日：2016-12-08

申请号：US14731480

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/45 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823871 ,  H01L21/283 ,  H01L21/28525 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7839 ,  H01L2221/1063

Abstract: A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

Abstract translation: 提供半导体器件中的沟槽接触外延层。 实施例包括在NFET和PFET区域中的源/漏区上形成通过层间电介质（ILD）的沟槽; 在所述ILD和所述沟槽中沉积保形氮化硅（SiN）层; 去除PFET区域中的SiN层; 在PFET区域的源极/漏极区域上生长锗（Ge）外延层; 在ILD和NFET和PFET区域的沟槽中沉积金属; 蚀刻NFET区域中的金属以暴露共形SiN层; 去除NFET区域中的SiN层; 在NFET区域的源极/漏极区域上生长III-V族外延层; 以及在ILD上和在NFET区域的沟槽中沉积金属。

公开(公告)号：US20160315182A1

公开(公告)日：2016-10-27

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160005867A1

公开(公告)日：2016-01-07

申请号：US14795716

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal K. KAMINENI ,  Ruilong XIE ,  Robert MILLER

IPC: H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

公开(公告)号：US20200295017A1

公开(公告)日：2020-09-17

申请号：US16298413

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien FROUGIER ,  Ruilong XIE

IPC: H01L27/11514 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.

公开(公告)号：US20200098913A1

公开(公告)日：2020-03-26

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Andre LABONTE ,  Daniel CHANEMOUGAME

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US20200083102A1

公开(公告)日：2020-03-12

申请号：US16685648

申请日：2019-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20190259667A1

公开(公告)日：2019-08-22

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.

公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190027578A1

公开(公告)日：2019-01-24

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala HARAN ,  Ruilong XIE ,  Balaji KANNAN ,  Katsunori ONISHI ,  Vimal K. KAMINENI

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/285

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US20180158931A1

公开(公告)日：2018-06-07

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.