公开(公告)号：US20080237887A1

公开(公告)日：2008-10-02

申请号：US11693651

申请日：2007-03-29

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/78302 ,  H01L2224/83855 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/48471 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad.

摘要翻译： 公开了一种半导体器件，其包括芯片接合焊盘，其加强以允许偏移堆叠焊盘的引线接合，即使在紧密偏移配置中。 在将第一裸片固定到基底之后，可以在第一衬底的一些或全部芯片接合焊盘上提供一层或多层电导体，以提高焊盘的高度。 导电层可以例如是使用已知的引线键合毛细管沉积在第一衬底的管芯接合焊盘上的导电球。 此后，可以添加第二管芯，并且可以使用在第一半导体管芯接合焊盘的凸起表面上安装引线接合球的公知的引线接合毛细管来实现第一管芯的引线接合。

公开(公告)号：US20080160674A1

公开(公告)日：2008-07-03

申请号：US11617689

申请日：2006-12-28

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L23/525 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer may be used to redistribute at least a portion of the bond pads from the first die in the pair to a second die in the pair. One die in each pair will be a working die and the other die in each pair will be a dummy die. The function of the integrated circuit beneath the redistribution layer on the dummy die is at least partially sacrificed.

摘要翻译： 公开了一种半导体器件及其形成方法，具有多个管芯再分配层。 在晶片上制造半导体管芯并且在从晶片分离之前，将相邻的半导体管芯配对在一起，并且跨越管芯对形成再分布层。 再分配层可以用于将至少一部分接合焊盘从该对中的第一管芯重新分布到该对中的第二管芯。 每对中的一个模具将是工作模具，并且每对模具中的另一个模具将是虚拟模具。 至少部分牺牲了虚设裸片上再分配层下面的集成电路的功能。

公开(公告)号：US20080157355A1

公开(公告)日：2008-07-03

申请号：US11617687

申请日：2006-12-28

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/48

CPC分类号： H01L25/0655 ,  H01L23/525 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer may be used to redistribute at least a portion of the bond pads from the first die in the pair to a second die in the pair. One die in each pair will be a working die and the other die in each pair will be a dummy die. The function of the integrated circuit beneath the redistribution layer on the dummy die is at least partially sacrificed.

摘要翻译： 公开了一种半导体器件及其形成方法，具有多个管芯再分配层。 在晶片上制造半导体管芯并且在从晶片分离之前，将相邻的半导体管芯配对在一起，并且跨越管芯对形成再分布层。 再分配层可以用于将至少一部分接合焊盘从该对中的第一管芯重新分布到该对中的第二管芯。 每对中的一个模具将是工作模具，并且每对模具中的另一个模具将是虚拟模具。 至少部分牺牲了虚设裸片上再分配层下面的集成电路的功能。

公开(公告)号：US20070155046A1

公开(公告)日：2007-07-05

申请号：US11321350

申请日：2005-12-29

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L21/00

CPC分类号： H01L23/49541 ,  G06K19/07732 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe design and methods for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.

摘要翻译： 公开了一种用于形成具有曲线形状的引线框半导体封装的引线框设计和方法。 引线框可以各自包括对应于精加工和分割半导体封装中的曲线边缘的一个或多个曲线槽。 在封装之后，面板上的集成电路封装可以通过将集成电路从引线框板切割成多个单独的集成电路封装而被分割。 引线框中的槽有利地允许使用仅制成直线切割的锯片来切割每个引线框。

公开(公告)号：US20070001285A1

公开(公告)日：2007-01-04

申请号：US11170883

申请日：2005-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L23/12

CPC分类号： H01L23/3121 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0271 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

摘要翻译： 公开了用于半导体封装的衬底的表面上的虚拟电路图案，该虚拟电路图形包括直线段，该直线段的长度受到控制，以便不在所述线段内产生高于所需应力的应力。 虚拟电路图案可以由线或邻接的或间隔开的多边形（例如六边形）形成。 虚拟电路图案的部分也可以形成为随机选择的取向，尺寸和位置。

公开(公告)号：US09064836B1

公开(公告)日：2015-06-23

申请号：US12852643

申请日：2010-08-09

申请人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

发明人： Chin-Tien Chiu ,  Shrikar Bhagath ,  Yuang Zhang ,  Lu Zhong ,  Kaiyou Qian

IPC分类号： H01L29/34 ,  H01L21/02

CPC分类号： H01L29/34 ,  B24B7/228 ,  B24B37/107 ,  H01L21/02024 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/3221 ,  H01L25/065 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor wafer, die and semiconductor package formed therefrom are disclosed, where the inactive surface of the wafer has an extrinsic gettering pattern formed from a texturing process. In examples, the texturing process follows a polishing process that removes stress concentration point from the inactive surface of the wafer.

摘要翻译： 公开了从其形成的半导体晶片，管芯和半导体封装，其中晶片的非活性表面具有由纹理化工艺形成的外在吸气图案。 在实例中，纹理化处理遵循从晶片的非活性表面去除应力集中点的抛光工艺。

公开(公告)号：US08432043B2

公开(公告)日：2013-04-30

申请号：US12165362

申请日：2008-06-30

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00015

摘要： A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

摘要翻译： 公开了一种低剖面半导体封装，其包括至少安装到衬底的第一和第二层叠半导体管芯。 第一和/或第二半导体管芯可以被制造成多个再分配焊盘，其形成在多个接合焊盘上并电耦合到多个接合焊盘。 在半导体管芯从晶片形成和切割之后，可以使用根据本发明的低剖面反向引线接合将管芯安装到衬底上。 特别地，在传统的反向接合工艺中，可以在导线和再分布垫之间形成楔形键，而不必在芯片接合焊盘上使用第二线接合球。

公开(公告)号：US20120009732A1

公开(公告)日：2012-01-12

申请号：US13235852

申请日：2011-09-19

申请人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

发明人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

IPC分类号： H01L21/56

CPC分类号： G06K19/07745 ,  G06K19/07732 ,  G11C5/04 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/0052 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

公开(公告)号：US08022519B2

公开(公告)日：2011-09-20

申请号：US11133576

申请日：2005-05-19

申请人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

发明人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

IPC分类号： H01L23/02

CPC分类号： G06K19/07745 ,  G06K19/07732 ,  G11C5/04 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/0052 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

摘要翻译： 一种基于系统的基于包的闪存卡，其包括集成电路封装，其占据卡内的小的整体区域并且被切割以符合卡的盖的形状。 集成电路可以从面板切割成适合于并符合成品存储卡（例如SD卡）的盖的形状的形状。 集成电路封装可以是系统级封装，多芯片模块或其中在单个封装中形成完整电子系统的其它布置。

公开(公告)号：US07791191B2

公开(公告)日：2010-09-07

申请号：US11617687

申请日：2006-12-28

申请人： Hem Takiar ,  Shrikar Bhagath

发明人： Hem Takiar ,  Shrikar Bhagath

IPC分类号： H01L23/48

CPC分类号： H01L25/0655 ,  H01L23/525 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer may be used to redistribute at least a portion of the bond pads from the first die in the pair to a second die in the pair. One die in each pair will be a working die and the other die in each pair will be a dummy die. The function of the integrated circuit beneath the redistribution layer on the dummy die is at least partially sacrificed.

摘要翻译： 公开了一种半导体器件及其形成方法，具有多个管芯再分配层。 在晶片上制造半导体管芯并且在从晶片分离之前，将相邻的半导体管芯配对在一起，并且跨越管芯对形成再分布层。 再分配层可以用于将至少一部分接合焊盘从该对中的第一管芯重新分布到该对中的第二管芯。 每对中的一个模具将是工作模具，并且每对模具中的另一个模具将是虚拟模具。 至少部分牺牲了虚设裸片上再分配层下面的集成电路的功能。