公开(公告)号：US20240030820A1

公开(公告)日：2024-01-25

申请号：US17870405

申请日：2022-07-21

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Eung San Cho ,  Danny Clavette

IPC: H02M3/158 ,  H02M3/157 ,  H02M3/335

CPC classification number: H02M3/1584 ,  H02M3/157 ,  H02M3/33571

Abstract: A power semiconductor module arrangement includes a circuit carrier including an electrically insulating substrate and an upper metallization layer disposed on upper side of the electrically insulating substrate, and a plurality of power stage inlays that each include first and second transistor dies and a driver die configured to control switching of the first and second transistor dies. Each of the power stage inlays are modular units comprising terminals that are electrically connected to the first and second transistor dies and the driver die. Each of the power stage inlays is embedded within the electrically insulating substrate. The upper metallization layer comprises conductive connectors that extend over the power stage inlays and connect with the terminals of the terminals of each of the power stage inlays.

公开(公告)号：US20210035879A1

公开(公告)日：2021-02-04

申请号：US16943054

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Thorsten Scharf

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.

公开(公告)号：US20200176412A1

公开(公告)日：2020-06-04

申请号：US16690948

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Andreas Grassmann

IPC: H01L23/00 ,  H01L21/56

Abstract: A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.

公开(公告)号：US10062671B2

公开(公告)日：2018-08-28

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H01L25/07 ,  H01L23/367 ,  H01L23/498 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

公开(公告)号：US20180096924A1

公开(公告)日：2018-04-05

申请号：US15821879

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US20150130071A1

公开(公告)日：2015-05-14

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L25/074 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract translation: 半导体封装包括包括多个半导体晶体管芯片的第一半导体模块和设置在半导体晶体管芯片上方的第一封装层，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个半导体驱动器通道和设置在半导体驱动器通道上方的第二封装层。 半导体驱动器通道被配置为驱动半导体晶体管芯片。

公开(公告)号：US20130328206A1

公开(公告)日：2013-12-12

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.