公开(公告)号：US20170179040A1

公开(公告)日：2017-06-22

申请号：US14978294

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Joshua D. Heppner ,  Mitul B. Modi ,  Anna M. Prakash

IPC: H01L23/552 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49524 ,  H01L23/552 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/97 ,  H01L2924/3025

Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.

公开(公告)号：US20170171957A1

公开(公告)日：2017-06-15

申请号：US14969514

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Nayandeep K. Mahanta ,  Joshua D. Heppner ,  Adel A. Elsherbini

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L23/34 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09854

Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.

公开(公告)号：US20160079150A1

公开(公告)日：2016-03-17

申请号：US14484896

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Michael Garcia ,  Kuang C. Liu ,  Rajasekaran Swaminathan

IPC: H01L23/498 ,  H01L23/36 ,  H01L21/48 ,  B23P15/26

CPC classification number: H05K7/20 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

Abstract translation: 本公开的实施例涉及与封装负载组件相关联的技术和配置。 在一个实施例中，包装负载组件可以包括框架，该框架被配置为围绕包装衬底的管芯区域形成周边，该封装衬底具有构造成与封装衬底的表面耦合的第一表面和与第一表面相对设置的第二表面 。 框架可以包括设置在第二表面上的可变形构件，其可以被配置为与散热器的底座相耦合，以经由框架分布施加在散热器和封装衬底之间的力，并且可以在应用 力，其可以允许散热器的底部接触在封装衬底的管芯区域内的集成散热器的表面。

公开(公告)号：US20150155092A1

公开(公告)日：2015-06-04

申请号：US14616508

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Robert L. Sankman ,  Brent S. Stone ,  Kaladhar Radhakrishnan ,  Joshua D. Heppner

IPC: H01F27/28 ,  H01F27/06 ,  H01F27/02

CPC classification number: H01F27/2852 ,  H01F17/045 ,  H01F27/02 ,  H01F27/027 ,  H01F27/06 ,  H01F27/2847 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T29/4902 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有围绕芯设置的一个或多个导电材料条的电感器结构。 条带可以在条的第一端和第二端处具有触点，并且可以在接触件之间具有间隙而围绕芯设置。 电感器结构可以安装在衬底的表面上，并且可以在衬底的表面中形成一个或多个迹线，以将两个或更多个导电材料条彼此电耦合以形成感应线圈。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10707171B2

公开(公告)日：2020-07-07

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita Yoshihiro ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US10446461B2

公开(公告)日：2019-10-15

申请号：US15816681

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/433 ,  H01L23/42 ,  H01L23/467

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

公开(公告)号：US20190074199A1

公开(公告)日：2019-03-07

申请号：US16083611

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sergio A. Chan Arguedas ,  Joshua D. Heppner ,  Jimin Yao

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.

公开(公告)号：US09953909B2

公开(公告)日：2018-04-24

申请号：US15212951

申请日：2016-07-18

Applicant: Intel Corporation

Inventor： Zuyang Liang ,  Michael Garcia ,  Joshua D. Heppner ,  Srikant Nekkanty

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/13

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01R13/2485

Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.

公开(公告)号：US20180019558A1

公开(公告)日：2018-01-18

申请号：US15716356

申请日：2017-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32 ,  H01L23/498

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20170179041A1

公开(公告)日：2017-06-22

申请号：US14978897

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Eric J. Li ,  Joshua D. Heppner

IPC: H01L23/552 ,  H01L23/29 ,  H01L23/528 ,  H01L21/56 ,  H01L21/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/768

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic component or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The vertical portions of the EMI shielding, including EMI shielding on the periphery may be formed by filling conductive ink in trenches formed in-situ with curing the molding. The top portion of the EMI shielding and the may additionally be cured conductive ink.