公开(公告)号：US20220390694A1

公开(公告)日：2022-12-08

申请号：US17338928

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Thu Ngoc Tran ,  Yew Fatt Kok ,  Kumar Abhishek Singh ,  Xiaoqian Li ,  Marely Tejeda Ferrari ,  Ravindranath Mahajan ,  Kevin Ma ,  Casey Thielen

IPC: G02B6/42

Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.

公开(公告)号：US20220373734A1

公开(公告)日：2022-11-24

申请号：US17323881

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Sandeep Gaan ,  Srinivas Pietambaram ,  Wenchao Li ,  Kristof Darmawikarta ,  Ankur Agrawal ,  Ravindranath Mahajan

IPC: G02B6/12 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  G02B6/13

Abstract: IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350° C., or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.

公开(公告)号：US20210296225A1

公开(公告)日：2021-09-23

申请号：US16827085

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Ravindranath Mahajan ,  Brandon Marin ,  Jeremy Ecton ,  Mohammad Mamunar Rahman

IPC: H01L23/50 ,  H01L29/06

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

公开(公告)号：US20210242104A1

公开(公告)日：2021-08-05

申请号：US17234671

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11011448B2

公开(公告)日：2021-05-18

申请号：US16529617

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US09713255B2

公开(公告)日：2017-07-18

申请号：US14184575

申请日：2014-02-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC: H01L23/13 ,  H05K1/14 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/49833 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/361 ,  H05K2201/09245 ,  H05K2201/09681 ,  Y10T29/49126

Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

公开(公告)号：US12272656B2

公开(公告)日：2025-04-08

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US12224103B2

公开(公告)日：2025-02-11

申请号：US17348580

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Matthew Tingey ,  Ravindranath Mahajan ,  Srinivas Pietambaram

IPC: H05K1/02 ,  G11B5/17 ,  H01F17/02 ,  H01F27/23 ,  H01F27/28 ,  H01F27/32 ,  H01L21/822 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H01L27/01 ,  H01L27/04 ,  H01L27/32 ,  H05K3/28

Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

公开(公告)号：US12199048B2

公开(公告)日：2025-01-14

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20240113087A1

公开(公告)日：2024-04-04

申请号：US17957403

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Gang Duan ,  Srinivas Pietambaram ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Debendra Mallik ,  Ravindranath Mahajan ,  Rahul Manepalli

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16235 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1094

Abstract: An apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. Other embodiments are also disclosed and claimed.