公开(公告)号：US20180097693A1

公开(公告)日：2018-04-05

申请号：US15283129

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shawna M. LIFF ,  Adel A. ELSHERBINI ,  Sasha N. OSTER ,  Feras EID ,  Georgios C. DOGIAMIS ,  Thomas L. SOUNART ,  Johanna M. SWAN

IPC: H04L12/24 ,  H01H57/00 ,  H01L41/047 ,  H01L41/187 ,  A61B5/0205 ,  A61B5/00

CPC classification number: H04L41/0816 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/02405 ,  A61B5/08 ,  A61B5/145 ,  A61B5/4266 ,  A61B5/4824 ,  A61B5/7282 ,  A61B5/7285 ,  A61B2560/0462 ,  H01H57/00 ,  H01L41/0471 ,  H01L41/187 ,  H01L41/1873 ,  H01L41/1876 ,  H04L41/0886

Abstract: Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the second electrical component. In an embodiment the encryption bank may include a plurality of portions that each have one or more switches integrated into the package substrate. In an embodiment each sensor transmits data to the second electrical component along different portions of the encryption bank. In some embodiments, the switches may be piezoelectrically actuated. In other embodiments the switches may be actuated by thermal expansion. Additional embodiments may include tri- or bi-stable mechanical switches.

公开(公告)号：US20160360618A1

公开(公告)日：2016-12-08

申请号：US14778027

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Aleksandar ALEKSOV ,  Sasha N. Oster ,  Shawna M. LIFF

IPC: H05K1/11 ,  H05K3/30 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H05K1/115 ,  H01L23/58 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/0286 ,  H05K1/144 ,  H05K1/181 ,  H05K3/303 ,  H05K3/368 ,  H05K2201/042 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09963 ,  H05K2201/10037 ,  H05K2201/10128 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10583 ,  H01L2924/00

Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.

Abstract translation: 一种装置，包括：基板，包括第一侧和相对的第二侧; 在衬底的第一侧上的至少一个第一电路器件，在衬底的第二侧上的至少一个第二器件; 以及在所述基板的第二侧上的支撑件，所述支撑件包括连接到所述至少一个第一和第二电路装置的互连件，所述支撑件具有可操作以从所述基板限定大于所述至少一个第一和第二电路装置的厚度尺寸的尺寸的厚度尺寸 一秒电路装置。 一种方法，包括在衬底的第一侧上布置至少一个第一电路部件; 在所述基板的第二侧上布置至少一个第二电路部件; 以及将支撑件耦合到所述衬底，所述衬底限定来自所述衬底的尺寸大于所述至少一个第二电路部件的厚度尺寸。

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

公开(公告)号：US20240213216A1

公开(公告)日：2024-06-27

申请号：US18597684

申请日：2024-03-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Amr Elshazly ,  Arun CHANDRASEKHAR ,  Shawna M. LIFF ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/49822 ,  H01L25/50

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20240021534A1

公开(公告)日：2024-01-18

申请号：US18374596

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Shawna M. LIFF ,  Adel A. ELSHERBINI ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US20220246554A1

公开(公告)日：2022-08-04

申请号：US17721241

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Javier A. FALCON ,  Shawna M. LIFF ,  Yoshihiro TOMITA

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20200303822A1

公开(公告)日：2020-09-24

申请号：US16635148

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Jimin YAO ,  Shawna M. LIFF ,  William J. LAMBERT ,  Zhichao ZHANG ,  Robert L. SANKMAN ,  Sri Chaitra J. CHAVALI

IPC: H01Q9/04 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66 ,  H01L23/498

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US20200212012A1

公开(公告)日：2020-07-02

申请号：US16639085

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Preston T. MEYERS ,  Javier A. FALCON ,  Shawna M. LIFF ,  Joe R. SAUCEDO ,  Adel A. ELSHERBINI ,  Albert S. LOPEZ ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L25/00

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.

公开(公告)号：US20190206782A1

公开(公告)日：2019-07-04

申请号：US15859331

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Siddarth KUMAR ,  Shawna M. LIFF

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.